RTL Engineer Memory Subsystem

Velaura•Santa Clara, CA

4d•$150,000 - $250,000•Hybrid

About The Position

We are looking for a talented RTL Engineer to help build Velaura's next-generation Physical AI SoC, with a focus on the high-speed, low-power memory subsystem that feeds the chip. In this role, you will work closely with architects, performance modelers, software engineers, verification engineers, physical design teams, and memory IP and PHY partners to transform innovative architectural concepts into production silicon. You will own significant portions of the memory subsystem design, contribute to microarchitectural decisions, and help deliver high-performance, power-efficient hardware that enables the next generation of intelligent physical systems. Physical AI workloads are memory-bound: bandwidth, latency, and power in the memory path directly gate what the chip can do. If pushing modern memory technologies to their limits at high speed and low power is the kind of problem you want to own, this role is for you.

Requirements

Experience designing RTL for complex digital systems, with hands-on ownership of memory subsystem blocks.
Demonstrated experience integrating a memory controller with a memory PHY, including controller-to-PHY interfaces such as DFI, initialization and training sequences, and bring-up.
Strong understanding of high-speed, low-power memory technologies such as LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, DDR, and HBM, including their protocol, timing, and power-state behavior.
Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
Expert-level Verilog and SystemVerilog skills and experience with modern RTL design methodologies, including lint, clock-domain crossing analysis, synthesis-aware coding, and low-power intent.
Familiarity with performance, power, and area tradeoffs in the memory path.
Strong debugging and problem-solving skills.
Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Nice To Haves

Familiarity with standard interconnect protocols such as AXI, CHI, and ACE on the controller's system-side interface, including quality-of-service mechanisms.
Experience with memory controller and PHY bring-up on silicon, including training and calibration debug and margining.
Knowledge of reliability, availability, and serviceability in the memory path, including inline and side-band ECC, scrubbing, poisoning, and error reporting.
Experience with low-power design techniques and power management architectures across memory and clock and power domains.
Experience developing a memory controller from the ground up, including command scheduling and arbitration, bank and rank management, refresh management, and reordering.
Knowledge of functional safety standards such as ISO 26262 and ASIL as they apply to memory-path design.
Experience with AI, machine learning, or edge AI hardware, especially the memory access patterns of tensor workloads.
Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.
Experience using modern AI tools and workflows to accelerate engineering productivity.

Responsibilities

Design, implement, and optimize RTL for the memory subsystem of the Velaura SoC, including memory controllers, fabric interfaces, and the logic that integrates with external memory PHYs.
Own memory controller and PHY integration, including controller-to-PHY interfaces such as DFI, initialization and training flows, calibration, and bring-up hooks.
Drive high-speed, low-power design of the memory path, including timing closure at high data rates, power-state management such as self-refresh and power-down modes, clock and power gating, and DVFS interactions.
Work with software teams to define hardware interfaces, memory maps, execution flows, and performance-critical interactions such as scheduling, prefetching, and quality of service.
Analyze bandwidth, latency, and utilization bottlenecks in the memory path and propose architectural and implementation improvements.
Optimize designs for performance, power, area, scalability, and reliability, including RAS features such as ECC and error reporting in the memory path.
Partner closely with verification and physical design teams throughout the development cycle, and with memory IP and PHY vendors during integration and silicon bring-up.
Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
Participate in design reviews and contribute to a culture of technical excellence.