RTL Design Engineer, Sr Staff

Qualcomm•Toronto, ON

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Qualcomm is expanding its team in connectivity networking products engineering Team. We are looking for experienced SoC RTL design engineers to contribute to our next generation connectivity networking products. This is an incredible opportunity to be part of the AI revolution and contribute to the complete semiconductor development cycle, from concept to product. The ideal candidate will have a strong and extensive background in RTL design across multiple projects. As an experienced RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with verification teams on achieving the code & functional coverage. You will work with Physical design team to meet area, power and performance goals. You will support physical design teams, verification teams, software teams and FPGA teams to ensure high quality SoC and ensure successful tapeout.

Requirements

Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Strong background with multi-year and multi-project experience in RTL SoC Design (Verilog/VHDL), and ASIC/FPGA debug methodologies
Proficient in reviewing high-level test plans and coverage metrics.
Expertise in Design Compiler Synthesis and formal verification using LEC.
Comprehensive understanding of timing closure.
Experience in post-silicon bring-up and debugging.
Team player with strong communication skills to ensure effective program execution.

Nice To Haves

Experience in SerDes PHY, DSP, and Analog mixed signal is desirable
Knowledge in Ethernet and PCIe standards is desirable
Ability to develop architecture and micro-architecture based on specifications.
Knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc.
Experience with memory controller designs and microprocessors is an advantage.
Knowledge of chip IO design and packaging is beneficial.

Responsibilities

Micro architect and RTL Design of SoC SubSystem/IP blocks
Will develop UPF and run CLP checks
Will be responsible for RTL quality checks - Lint/CDC/LEC
Create appropriate documentation for hardware blocks
Responsible for analyse / debug / fixing issues reported by verification team
Will develop the synthesis constraints for the blocks / subsystem
Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation