VLSI RTL design engineer

Advanced Micro Devices, Inc•Fort Collins, CO

12h•Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. AMD’s Cores Organization delivers industry leading CPU’s, Caches, and Chiplets that are the foundation of AMD’s server, client, and gaming business. We are looking for an experienced VLSI RTL design engineer to join this innovative team. In this role, the candidate will invent and implement the highest performance, most energy efficient cache and fabric designs in the industry. The candidate will have the potential and will develop to be a key contributor and leader for AMD’s next generation cores and caches. The candidate will join the team based in Fort Collins, CO.

Requirements

BS/MS in EE, CS, CSE (or similar), plus 3+ years hardware design experience

Nice To Haves

Prior SRAM, Coherent Cache or interconnect/NOC RTL design experience
Prior experience with Digital RTL Design, Verilog HDL, Software Development, and Scripting

Responsibilities

Collaborate with Cache and CPU Architects to design, document, and execute optimized high-performance Cache and Routing Fabric designs.
Collaborate with Physical Design to develop RTL that is optimized for physical construction and timing closure.
Collaborate with Design Verification to develop architecture and features that are documented clearly and are verifiable.
Collaborate with Design For Test teams to develop RTL that is reliable, testable, and manufacturable.
Work across global teams to solve complex architectural interactions between IP and SOC designs
Develop ways to improve our CPU design by increasing quality, by simplifying design complexities through innovation, and by improving our technical interactions with other teams
Solve design and tool problems requiring ground-breaking approaches and champion innovation across the organization.
Create technical presentations for peers and management.