Staff RTL Design Engineer - CPU LS/PF/MMU

SiFive•Austin, TX

3d•$178,848 - $218,592

About The Position

As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-standard RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Requirements

BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
3+ years of design experience.
Academic or professional experience with CPU RTL design.
Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
Strong software engineering skills/background, including: Object-oriented, aspect-oriented, and particularly functional programming
Test-driven development, particularly ability to write adaptive unit tests
Attention to detail and a focus on high-quality design.
Good verification principles, SVA, and coverage.
Ability to work well with others and share the belief that engineering is teamwork.

Nice To Haves

Experience with Scala/Chisel, Bluespec, or some other language/DSL for generating configurable hardware via software.
Knowledge of RISC-V instruction set architecture.
Expertise in out-of-order processor micro-architecture, design, and verification in one or more of the following areas: load-store unit, coherent caches, cache prefetching, virtual memory MMU/TLBs.
Familiarity with Git/Github, Jira, Confluence.

Responsibilities

Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
Microarchitecture development and specification.
Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.