Product Test Technician

Texas Instruments•Lehi, UT

About The Position

Texas Instruments is seeking a detail-oriented and analytical Product Development Engineering (PDE) Product Test Technician to join our LFAB team. This role serves as a critical "Quality Gatekeeper" within our wafer fabrication process. You will be responsible for the visual and statistical inspection of wafer maps to identify defect patterns (signatures), ensuring that only high-quality material proceeds to final testing and our customers. This is not just repetitive execution of manual tasks; it is a technical role that requires high-level pattern recognition, logical troubleshooting, and a mindset geared toward automation. As you grow in this role, you will transition from executing established protocols to consulting with engineers on process improvements and utilizing AI-driven automation to streamline manufacturing workflows.

Requirements

Associate’s degree in a technical field or equivalent semiconductor manufacturing experience.
2+ years of equivalent experience to high-volume semiconductor manufacturing.
Advanced Excel Proficiency: Ability to import external data, use Pivot Tables, build complex charts, and utilize data validation.
Strong analytical and critical thinking skills with an exceptional eye for detail.
Ability to thrive in an "interrupt-driven" environment, managing urgent engineering requests alongside routine tasks.

Nice To Haves

Experience with data visualization tools (e.g., Spotfire , Tableau).
Experience with database querying (e.g., SQL ).
Exposure to automation/scripting logic (e.g., Python, Perl) or an interest in using AI to develop automation tools.
Familiarity with parametric test data and the relationship between wafer-level testing and final product yield.
Basic Linux Skills: Familiarity with command-line navigation (SSH, VNC, directory navigation, and command execution).

Responsibilities

Perform high-level inspection of wafer maps (PNG die-level images) to identify defect "signatures."
Compare observed patterns against a technical Wafer Map Library to determine if failures are representative of known device issues.
Execute "Inking" protocols to exclude suspect dies (Post Probe Outliers) from moving to the next manufacturing stage, preventing "underkill" (shipping bad parts) and "overkill" (unnecessary scrap).
Monitor Statistical Bin Limits (SBL) and Common Probe Outlier (CPO) thresholds.
Identify gaps in automated detection and escalate findings to PDE Engineers for further analysis.
Act as a technical liaison between PDE and back-end Probe Sites.
Provide logistical priority updates and technical troubleshooting support (e.g., identifying hardware-related probe touchdown issues via dashboard analysis).
Maintain the Wafer Map Library (Confluence) and prepare technical documentation for Qualification Lots, including baseline yield reviews and hold status reports.
Identify opportunities for continuous improvement.
Investigate "misses" in the process and utilize Data Analysis skills to Pareto and characterize the issues and develop procedures to close gaps.
Identify opportunities to automate repetitive tasks.