Product Test Technician

Texas Instruments•Lehi, UT

2d•Onsite

About The Position

Texas Instruments is seeking a detail-oriented and analytical Product Development Engineering (PDE) Product Test Technician to join our LFAB team. This role serves as a critical "Quality Gatekeeper" within our wafer fabrication process. You will be responsible for the visual and statistical inspection of wafer maps to identify defect patterns (signatures), ensuring that only high-quality material proceeds to final testing and our customers. This is not just repetitive execution of manual tasks; it is a technical role that requires high-level pattern recognition, logical troubleshooting, and a mindset geared toward automation. As you grow in this role, you will transition from executing established protocols to consulting with engineers on process improvements and utilizing AI-driven automation to streamline manufacturing workflows.

Requirements

Detail-oriented and analytical mindset
High-level pattern recognition skills
Logical troubleshooting abilities
Mindset geared toward automation
Ability to consult with engineers on process improvements
Experience utilizing AI-driven automation
Experience with wafer maps (PNG die-level images)
Familiarity with a technical Wafer Map Library
Experience with "Inking" protocols
Understanding of "underkill" and "overkill" concepts
Ability to monitor Statistical Bin Limits (SBL) and Common Probe Outlier (CPO) thresholds
Ability to identify gaps in automated detection
Experience escalating findings to PDE Engineers
Technical liaison experience between PDE and back-end Probe Sites
Ability to provide logistical priority updates
Technical troubleshooting support experience
Experience with dashboard analysis
Experience maintaining a Wafer Map Library (Confluence)
Experience preparing technical documentation for Qualification Lots
Experience with baseline yield reviews
Experience with hold status reports
Ability to identify opportunities for continuous improvement
Experience investigating "misses" in a process
Data Analysis skills
Experience with Pareto analysis
Ability to characterize issues
Ability to develop procedures to close gaps
Ability to identify opportunities to automate repetitive tasks

Responsibilities

Perform high-level inspection of wafer maps (PNG die-level images) to identify defect "signatures." Compare observed patterns against a technical Wafer Map Library to determine if failures are representative of known device issues.
Execute "Inking" protocols to exclude suspect dies (Post Probe Outliers) from moving to the next manufacturing stage, preventing "underkill" (shipping bad parts) and "overkill" (unnecessary scrap).
Monitor Statistical Bin Limits (SBL) and Common Probe Outlier (CPO) thresholds. Identify gaps in automated detection and escalate findings to PDE Engineers for further analysis.
Act as a technical liaison between PDE and back-end Probe Sites. Provide logistical priority updates and technical troubleshooting support (e.g., identifying hardware-related probe touchdown issues via dashboard analysis).
Maintain the Wafer Map Library (Confluence) and prepare technical documentation for Qualification Lots, including baseline yield reviews and hold status reports.
Identify opportunities for continuous improvement. Investigate "misses" in the process and utilize Data Analysis skills to Pareto and characterize the issues and develop procedures to close gaps. Identify opportunities to automate repetitive tasks.