Product Test Engineer

Lattice Semiconductor • Hillsboro, OR

12h

About The Position

Product Test Engineering is part of Lattice’s Manufacturing Operations group and is the link between Silicon Design and Volume Production. Its primary mission is to define and develop full chip verification and validation content to enable leading ATE manufacturing capability with world-class cost and quality levels for all new products at Lattice. Product Test Engineers are involved in the early feasibility stage of product development to assure proper planning for both Design for Test and Design for Manufacturability. Test planning also involves the selection and or development of the test equipment to be used in Manufacturing to achieve cost and quality goals. Product Test Engineering develops all ATE full chip verification tests prior to tape out and then validates the yield and performance of the product over temperature, voltage and wafer process variation. Test coverage goals, metrics, fault grading, and test coverage are critical activities of PTE. Product Test Engineering develops and transfers a complete manufacturing solution to Lattice’s worldwide Operations Group. Product Test Engineering needs innovative and high energy individuals to execute the tasks required to meet our objectives. The job develops very broad knowledge, and technical skill sets in the semiconductor industry as it is involved in every stage of product development. Thus, candidates need to possess the ability to acquire new skills and expertise rapidly. Communication skills are critical, since the Product Test Engineering team has key interactions with every other technical group in the company including Design, Applications, System Validation, Software, Manufacturing, Product Engineering, Marketing, Quality and Reliability.

Requirements

• BS degree (Electrical, Electronics or Computer Engineering) with 8 years of industry experience, or MS degree (Electrical, Electronics or Computer Engineering) with 6 years of industry experience
• Good working knowledge of semiconductor devices and test methodologies
• Experience in ATE test program development, integration and debug on Nextest Magnum, Advantest T2K or Teradyne UltraFLEX preferred.
• Experience in IC characterization and/or failure analysis using various bench tools (i.e. Oscilloscope, Pattern Generators, Data Timing Generator, Multimeters, etc)
• Experience with WAT/etest, wafer sort, package assembly, final test (i.e. full backend IC process)
• Experience in Programmable Logic is desired
• Experience in RTL Design, Design Verification an advantage
• Knowledge in test, DFT methodologies (ie. scan, BIST), memory test, and fault grade methodologies an advantage
• Knowledge in Hardware Description Language such as Verilog or VHDL an advantage
• Knowledge in programming languages (ie. Python, C++)
• Excellent verbal and written skills.
• Demonstrated ability to work with multiple groups and across cultures
• Good analytical and problem-solving abilities
• Strong Windows, Unix, and MS Office skills
• Curious with strong self-motivation to learn and explore

Nice To Haves

• Experience in Programmable Logic is desired
• Experience in RTL Design, Design Verification an advantage
• Knowledge in test, DFT methodologies (ie. scan, BIST), memory test, and fault grade methodologies an advantage
• Knowledge in Hardware Description Language such as Verilog or VHDL an advantage

Responsibilities

• Develop test plans using established methodologies targeted on chip IP functions and features.
• Design and implement test circuits using FPGA fabric and embedded IP using Lattice’s proprietary design SW.
• Develop scripts to automate test generation and own Pre-Si verification of content to ensure Si readiness.
• Execute Post-Si pattern validation using wafer-level ATE, package-level ATE, and package-level bench platforms across process, temperature, and voltage conditions.
• Identify and analyze to root cause product marginalities, communicating and coordinating root cause closure to appropriate cross-functional team (eg. Applications Engineering, Design Engineering, etc.)
• Take ownership of IP content development and drive any issues to resolution.
• Plan and execute test content delivery to meet or exceed schedules required for internal and external customers samples.
• Extract coverage metrics of test patterns using fault grading and review for coverage improvements.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior