Principal Test Engineer/DFT Architect

Renesas Electronics•Austin, TX

11h•Onsite

About The Position

The Principal Test / DFT Architect will define testability and production test strategy for advanced semiconductor products from concept through production release. This role bridges ATE test architecture, DFT, circuit design, product engineering, validation, quality, operations, and manufacturing to ensure products are designed for high-quality, cost-effective, scalable production test. The ideal candidate has deep semiconductor ATE test experience, strong knowledge of analog, mixed-signal, digital, and power-management IC testing, and enough circuit design understanding to influence observability, controllability, trim/calibration strategy, test muxing, embedded monitors, diagnostic coverage, and test strategy before tape-out. This is a senior technical leadership role for an individual contributor who can set strategy, influence design and engineering teams, mentor engineers, and establish reusable test and DFT methodologies across product families.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field; advanced degree preferred.
Typically 12+ years of semiconductor experience in test engineering, DFT, product engineering, validation, design, or product industrialization.
Strong hands-on experience with ATE test development and production test strategy.
Experience with analog, mixed-signal, digital, and/or power-management IC test.
Strong understanding of ATE instrumentation, timing, digital pattern execution, analog measurements, multisite test, handler/prober interfaces, test hardware, and production data.
Working knowledge of circuit design concepts, including references, regulators, ADC/DACs, digital interfaces, clocks, trims, NVM/fuse structures, protection features, and test-access circuitry.
Familiarity with wafer sort/final test strategy, production test flows, yield learning, quality screening, and test-cost modeling.
Ability to read schematics, block diagrams, design specs, register maps, test plans, and characterization/yield data.
Strong debug capability using ATE results, bench measurements, simulation data, failure-analysis inputs, and production trends.
Experience with scripting, automation, and data analysis tools such as Python, JMP, MATLAB, SQL, or equivalent.
Demonstrated ability to lead cross-functional technical reviews and influence without direct authority.

Nice To Haves

Experience with power-management, automotive, high-voltage, mixed-signal, or digitally assisted analog products.
Experience with ATE platforms such as Advantest V93K, Teradyne/Microflex, ETS, COHU/DiamondX, SPEA, or similar.
Familiarity with scan, BIST, memory test, boundary scan, test access protocols, and digital DFT methods.
Experience with trim/calibration architecture, fuse/NVM programming, wafer sort, final test, production diagnostics, and test-time reduction.
Knowledge of NPI gates, production release, characterization, qualification, GRR, and test readiness.
Experience with yield analysis, guardbanding, statistical methods, test-cost modeling, quality screening, and production data analysis.
Familiarity with AI/ML or advanced analytics applied to semiconductor test and production data is a plus.

Responsibilities

Define product-level test and DFT strategy, including wafer probe, final test, characterization, qualification, GRR, production test flow, and cost-of-test targets.
Partner with design, systems, validation, product engineering, test engineering, quality, operations, and manufacturing teams to define DFT requirements early in the lifecycle.
Drive requirements for test muxes, scan/debug access, analog observability, digital controllability, embedded monitors, BIST where applicable, trim/calibration access, fuse/NVM test modes, and diagnostic hooks.
Review schematics, architecture documents, specifications, register maps, and test-mode plans to identify testability gaps before design freeze.
Establish reusable DFT and test-access standards for power, analog, mixed-signal, and digitally assisted products.
Define ATE platform strategy, including tester selection, instrument usage, multisite targets, handler/prober compatibility, hardware reuse, test-time optimization, and production scalability.
Establish strategic test flows, binning methodology, screen strategy, guardband approach, data collection strategy, and test naming conventions.
Assess feasibility for critical tests such as high-voltage stress, analog parametric measurements, digital interface testing, trim/calibration, NVM programming, wafer-level characterization, and production diagnostics.
Influence test hardware architecture, including load boards, probe cards, sockets, change kits, and interface circuitry, to improve accuracy, signal integrity, and multisite scalability.
Guide platform-transition strategies and production test readiness for new products and product families.
Apply circuit-level knowledge to ensure key internal nodes, bias conditions, clocks, references, protection circuits, calibration loops, and failure mechanisms are observable and controllable on ATE.
Work with design teams to ensure critical analog, digital, and power-management functions can be accurately measured in production.
Evaluate the impact of circuit architecture, wafer-test strategy, package choice, and test platform capability on test coverage, yield learning, quality risk, cost, and cycle time.
Support complex silicon and production debug by connecting ATE data, bench data, circuit behavior, design intent, process variation, and production yield trends.
Identify testability risks early, including limited test access, insufficient characterization coverage, weak diagnostics, limited traceability, or late test-mode definition.
Serve as senior technical interface between design, DFT, test engineering, product engineering, validation, quality, operations, and manufacturing partners.
Lead testability reviews at key development gates and ensure issues are resolved before tape-out, qualification, or production release.
Create test architecture documentation, DFT checklists, coverage expectations, production-readiness criteria, and product-family test strategy templates.
Mentor engineers on DFT principles, ATE methodology, debug strategy, and scalable production test development.
Influence roadmap decisions for ATE platforms, test data infrastructure, characterization automation, production analytics, and AI-enabled test optimization.