DFT Engineer

Qualcomm • San Diego, CA

3d • $140,000 - $210,000

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. The Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs. The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies. The candidate should have solid hands-on experience with industry standard DFT techniques such as scan and MBIST. Job responsibilities include DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations. The ideal candidate will have experience in both pre, and post-silicon in the DFT domain. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

Requirements

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Solid hands-on experience with industry standard DFT techniques such as scan and MBIST.

Nice To Haves

• 10+ years industry experience in the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power and multi voltage domain designs.
• A strong fundamental knowledge of DFT is required
• Understanding of core-based test methodology and scan isolation.
• Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.
• Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing.
• Experience with industry EDA ATPG and insertion tools.
• Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis.

Responsibilities

• Implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs.
• Deployment of DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies.
• DFT pattern generation, coverage analysis and debug.
• Running and debugging gate level simulations.
• Experience in both pre, and post-silicon in the DFT domain.

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support your success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior