DFT Engineer, Principal

Qualcomm • Toronto, ON

1d

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm DFT Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Requirements

• Bachelor's degree in engineering science, Electrical and Computer Engineering or Computer Science
• 10+ years of experience in complex SoC designs in RTL, DFT or FE capacity.
• Vast experience with various DFT EDA tools from Siemens, SNPS and Cadence
• Good knowledge and understanding in Verilog/VHDL and SystemVerilog
• Exposure to CAD and automation.
• Good exposure for using de-Perl techniques in creating generic codes.
• Knowledge of TCL and Python is a plus.
• Extensively experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs)
• Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences.

Nice To Haves

• Track record in integrating custom made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs is highly desirable.

Responsibilities

• Acting as a member of Qualcomm's central DFT methodology group responsible for developing, maintaining and supporting flows across all company business units and projects
• Architecting methodologies and flows for an integrated, RTL centric "shift left" DFT environment across company IPs, ASICs and SoC designs.
• Writing and automating RTL for advanced DFT and DFD features not currently supported by the EDA vendors
• Developing automated verification test bench and sequence creation for DFT IP. Architecting end-2-end verification solutions from static design checks, through formal and sequence-based verification.
• Building IP/block and SoC level scan insertion flows and scripting ATPG retargeting procedures. Creating automated QoR checks for implementation quality control.
• Writing static timing constraints, creating waivers and devising flows for bullet proof timing checks.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal