Principal Solutions Architect – Semiconductor Test

NVIDIA • Santa Clara, CA

6d • $216,000 - $345,000

About The Position

NVIDIA is seeking a Staff/Principal Solutions Architect to define and lead technical strategy for semiconductor testing across wafer and package operations. This senior individual-contributor role supports manufacturing and product engineering teams, leading the architectural vision for device testing from wafer probe through final package test. The role focuses on modernizing test infrastructure, improving yield, and embedding data-driven intelligence throughout the test lifecycle. The architect partners with development, process, product engineering, and manufacturing teams across sites to scale test strategy for increasingly complex device portfolios.

The expected base salary range is USD 216,000–345,000, determined by location, experience, and other objective job-related factors. The role is also eligible for equity and benefits. Applications will be accepted at least until November 3, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes and is an equal opportunity employer committed to an inclusive work environment.

Requirements

• 15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
• Extensive knowledge in at least three of the following areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
• Experience with leading ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar systems.
• Strong background in DFT architectures, including scan compression, MBIST, LBIST, JTAG, and related methodologies.
• Proficiency in test-related scripting and automation using Python, Perl, C++, or platform-native languages.
• Proven ability to lead multi-site technical initiatives involving multifunctional teams and influence without direct authority.
• MSEE, MSCE, MSCS, or a related field, or equivalent experience.

Nice To Haves

• Experience with mixed-signal, RF, or high-speed I/O test.
• Experience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test.
• Knowledge of test data formats such as STDF and ATDF, and analytics tools such as JMP, Spotfire, or custom tools.
• Exposure to advanced packaging test challenges, including 2.5D/3D, chiplets, and KGD.
• Prior engagement with SEMI standards committees or ATE vendor co-development programs.
• Ph.D. or equivalent experience in a related field.

Responsibilities

• Define test development strategy across wafer-level probe/ATE and package, final, and qualification testing for new and existing product families.
• Lead architectural trade-off decisions involving test coverage, test time, cost of test, and quality escapes across the test flow.
• Establish architectural guidelines for test programs, Test Methods/Class structure, modularity, and reuse across ATE platforms.
• Serve as senior liaison between build and test engineering on DFT architecture decisions, including scan, BIST, JTAG, boundary scan, and embedded compression.
• Influence SoC and IP build reviews to ensure testability, observability, and debug-ability.
• Drive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization.
• Define and maintain test roadmaps aligned with device technology roadmaps and manufacturing scale targets.
• Mentor senior and principal test engineers and develop technical standards and guidelines across the test organization.
• Engage with ATE vendors, test IP providers, and industry consortia on emerging standards and technology directions.

Benefits

• Competitive salaries and a generous benefits package.
• Equity eligibility.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior