Principal Signal Integrity Engineer – R&D Networking Platforms

Hewlett Packard Enterprise • Roseville, CA

9d • $158,000 - $321,000 • Onsite

About The Position

Hewlett Packard Enterprise is seeking a Principal Signal Integrity Engineer to provide technical leadership for signal and power integrity across networking platforms and future technology generations. The role is the organization’s technical authority for SI/PI, influencing architecture, design methodologies, engineering standards, and technology roadmaps for enterprise and AI networking infrastructure.

The engineer will define SI/PI strategy and lead architecture for next-generation networking systems, including high-speed interfaces and leading-edge SerDes technologies. The role spans concept through production and includes establishing scalable design guidelines, simulation and validation approaches, resolving complex technical issues, evaluating emerging technologies, and partnering with ASIC, package, PCB, mechanical, thermal, and system architects. The engineer will also mentor colleagues, contribute to innovation through patents and industry engagement, and serve as the final escalation point for critical SI/PI decisions.

This position is designated onsite, with an expectation that the employee will primarily work from an HPE office. The expected U.S. base salary range is $158,000–$321,000 annually in California; variable incentives may also be offered. Actual compensation may vary based on location, experience, education, training, and skills.

Requirements

• Bachelor’s, master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• 15 or more years of experience in signal integrity, power integrity, package design, PCB design, and high-speed system architecture.
• Recognized expertise in high-speed digital system design, including electromagnetic theory, transmission-line behavior, crosstalk, loss mechanisms, jitter, equalization, and channel optimization.
• Extensive experience architecting and validating high-speed systems using advanced SerDes technologies and complex networking platforms.
• Demonstrated success leading SI/PI strategies across multiple large-scale product developments from concept through production.
• Expert knowledge of SI/PI simulation methodologies, including time-domain, frequency-domain, statistical, BER, and electromagnetic analysis.
• Deep expertise with industry-standard tools such as Synopsys HSPICE, Keysight ADS, Ansys HFSS, SIwave, PowerSI, and Cadence design environments.
• Extensive experience defining PCB stackups, design constraints, routing architectures, power distribution networks, and signal-integrity requirements for high-volume products.
• Hands-on expertise with laboratory instrumentation including VNAs, TDRs, high-bandwidth oscilloscopes, spectrum analyzers, and compliance test equipment.
• Proven ability to correlate simulation results with laboratory measurements and improve modeling accuracy and design predictability.
• Strong understanding of system-level interactions among signal integrity, power integrity, thermal performance, electromagnetic compatibility, and manufacturability.

Nice To Haves

• Demonstrated technical leadership across geographically distributed engineering teams.
• Ability to influence architecture and engineering decisions across organizations without direct authority.
• Track record of mentoring engineers and developing technical capabilities within an organization.
• History of innovation through patents, publications, industry collaboration, or significant technical contributions.
• Excellent communication and presentation skills, including the ability to explain complex technical concepts to engineers, architects, executives, and customers.
• Strong business and engineering judgment, balancing technical excellence with schedule, product cost, risk, and scalability.
• Self-directed leadership and ability to define technical direction in highly ambiguous environments.

Responsibilities

• Define and drive SI/PI technical strategy, methodologies, design standards, and engineering best practices across networking hardware platforms.
• Lead signal and power integrity architecture for next-generation networking systems, influencing platform design from concept through production.
• Provide technical leadership for high-speed interfaces, including next-generation SerDes technologies.
• Establish SI/PI design guidelines, PCB stackup strategies, routing methodologies, and validation approaches.
• Lead cross-functional technical reviews and resolve complex SI/PI challenges across products and engineering disciplines.
• Develop advanced simulation methodologies, modeling approaches, and automation techniques to improve productivity and design quality.
• Drive SI/PI technology readiness for future networking products by evaluating emerging technologies and enabling new architectures and materials.
• Lead root-cause investigations of field, validation, and manufacturing issues involving signal integrity, power integrity, timing, and electromagnetic interactions.
• Partner with ASIC, package, PCB, mechanical, thermal, and system architects to optimize end-to-end electrical performance.
• Champion technical innovation through patents, industry engagement, publications, and contributions to next-generation technology development.
• Mentor and develop engineers across multiple sites and build organizational SI expertise.
• Serve as the final escalation point for critical SI/PI decisions, balancing performance, risk, schedule, and product cost.

Benefits

• Comprehensive benefits intended to support employees’ and their loved ones’ physical, financial, and emotional wellbeing.
• Career-development programs supporting growth as a subject-matter expert or movement to another division.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal