Principal SerDes Design Engineer

Celero Communications • San Jose, CA

3d

About The Position

We are looking for a SerDes Lead Designer to help deliver high-speed interconnect technology for next-generation AI. The role offers the opportunity to architect and design SerDes for next-generation transceivers. The engineer will define architecture, specifications, and circuit topologies; oversee system-level modeling and signal and power integrity analysis; design analog/mixed-signal circuits and key SerDes blocks; and lead lab validation, debugging, characterization, and performance optimization. The role also involves overseeing physical layout, correlating silicon measurements with simulation, and working cross-functionally to deliver IP for seamless SoC integration.

Requirements

• Master’s degree and/or PhD in Electrical Engineering or a related field.
• 10+ years of relevant experience in SerDes design.
• Proven record of taking high-speed SerDes designs through tape-out and into volume production.
• Experience with lab bring-up, characterization, and debugging of designs that reach production.
• Extensive experience with advanced process technologies, including 16nm/12nm, 7nm, 5nm, 3nm, or 2nm.
• Experience interacting cross-functionally to deliver IP and ensure seamless SoC integration.
• Strong communication and documentation skills.

Responsibilities

• Define architecture, specifications, and circuit topologies for next-generation SerDes.
• Oversee system-level behavioral modeling using tools such as MATLAB, SystemVerilog, and Verilog-A to analyze link budgets, equalization strategies, and jitter budgets.
• Design high-performance analog/mixed-signal circuits in advanced process technologies.
• Develop and oversee critical blocks, including RX/TX equalization (CTLE, DFE), high-speed PLLs, phase interpolators, DLLs, and TDCs.
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve power, performance, and area.
• Oversee physical layout to minimize parasitics, device stress, electromigration, and process-variation impacts.
• Oversee signal-integrity and power-integrity analysis to meet system-defined targets.
• Lead lab validation, debugging, and characterization of SerDes IP in the company's lab.
• Correlate silicon measurements with simulated data and lead performance optimization in the system environment.
• Work cross-functionally to deliver IP and ensure seamless integration in SoCs.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal