Principal RF/mmWave IC Layout Design Engineer – TeraWave

Blue Origin•San Diego, CA

4d•$269,175 - $376,844•Onsite

About The Position

Blue Origin is seeking a Principal RF/mmWave IC Layout Design Engineer to lead physical implementation and top-level integration of RF/mmWave integrated circuits for advanced payloads, terminals, and next-generation communication systems. The role focuses on custom layouts for high-performance RF, mmWave, analog, and mixed-signal ICs, with responsibility for block-level execution, chip-level planning, physical verification, parasitic optimization, and tape-out readiness. The engineer will work closely with RFIC, analog, and mixed-signal teams and provide technical leadership through layout methodology, mentoring, and coordination across internal and external teams. The position supports Blue Origin’s TeraWave satellite communications network. The role is based onsite in San Diego, California (preferred), or Cupertino, California. Relocation is provided, travel is expected up to 10% of the time, and interviews include a technical assessment. Applications are accepted on an ongoing basis until the requisition is closed.

Requirements

Bachelor’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, or a related technical field.
10 or more years of professional experience in RF/mmWave, analog, or mixed-signal custom IC layout and physical implementation.
Extensive hands-on experience with high-frequency RF/mmWave IC layout in RF CMOS, SOI, SiGe, or related advanced semiconductor processes.
Successful completion of multiple IC product lifecycles or tape-outs, preferably including high-volume or mission-critical chipsets.
Strong expertise in layout and integration of RF transmitter and receiver front-end circuits, including one or more full TX/RX chains.
Direct experience laying out RF/mmWave blocks such as LNAs, PAs, mixers, VCOs, frequency synthesizers, phase shifters, VGAs, multipliers, and RF passives.
Strong understanding of device-level layout techniques, including matching, symmetry, shielding, common-centroid layout, interdigitation, guard rings, and isolation structures.
Strong understanding of parasitic effects, coupling mechanisms, grounding strategies, substrate noise isolation, differential routing, and RF signal integrity.
Experience with analog building blocks such as operational amplifiers, bias generators, temperature sensors, LDOs, ADCs, DACs, and related support circuitry.
Strong understanding of physical design sign-off flows, including LVS, DRC, ERC, parasitic extraction, EM/IR analysis, current density, and electromigration requirements.
Proficiency with IC layout and verification tools such as Cadence Virtuoso/Virtuoso XL, Siemens Calibre, Quantus, EMX, or equivalent tools.
Experience with top-level integration, including floorplanning, hierarchical integration, ESD, pad integration, density fill, DFM, and tape-out preparation.
Strong communication skills and demonstrated ability to work independently on complex layout challenges while influencing technical direction across teams.
Must be a U.S. citizen or national, U.S. permanent resident/current Green Card holder, or lawfully admitted into the U.S. as a refugee or granted asylum.

Nice To Haves

Prior experience managing or technically leading a layout team, including mentoring layout engineers and coordinating multiple contributors.
Experience with beamforming front-end ICs, phased-array architectures, or highly integrated RF/mmWave transceivers.
Experience with high-performance IC development using III-V technologies such as GaAs or GaN.
Experience implementing and optimizing RF passive structures, including inductors, transformers, capacitors, transmission lines, baluns, and matching networks.

Responsibilities

Lead physical design and implementation of RF/mmWave ICs, including transmitter and receiver front-end and supporting analog/RF blocks.
Drive block-to-top integration, including chip-level floorplanning, power and ground planning, signal routing, ESD strategy, pad assembly, density fill, and design-for-manufacturability requirements.
Develop chip-level integration approaches that optimize RF performance, isolation, area, reliability, and manufacturability.
Perform and debug physical verification, including DRC, LVS, ERC, antenna checks, density checks, and related sign-off requirements.
Support parasitic extraction and post-layout analysis, collaborating with circuit designers to resolve performance, coupling, EM, IR, reliability, and extraction-related issues.
Develop layout schedules, identify implementation risks and dependencies, and deliver verified layouts aligned with program milestones and tape-out schedules.
Prepare and release final layout databases to the foundry, and support tape-out readiness reviews and mask database delivery.
Lead layout reviews, define and document best practices, and mentor less-experienced layout engineers and designers.
Coordinate layout execution across internal teams, third-party design partners, and cross-functional stakeholders across multiple locations.

Benefits

Medical, dental, and vision insurance.
Basic and supplemental life insurance.
Paid parental leave.
Short- and long-term disability.
401(k) with company match of up to 5%.
Education Support Program.
Stock options for regular employees working at least 20 hours per week.
Paid time off of up to four weeks per year based on weekly scheduled hours.
Up to 14 company-paid holidays.
Depending on role type and job level, employees may be eligible for benefits and bonuses based on individual contributions and company results or other factors.