Principal PIC (Photonic Integrated Circuit) Design Engineer

Voyant Photonics•New York, NY

1d•$200,000 - $280,000•Onsite

About The Position

Voyant Photonics is hiring a Principal PIC Design Engineer to lead the development of large-scale silicon photonic integrated circuits for optical circuit switching in AI data centers and chip-scale FMCW LiDAR. The role spans system architecture, photonic device and circuit design, layout, foundry tapeout, and characterization. The engineer will architect complex photonic systems, define chip-level specifications and trade-offs, and work with a multidisciplinary team in a fast-paced startup environment. The position involves integrating hundreds to thousands of active and passive photonic devices, defining optical architectures and link budgets, managing chip integration and design-for-manufacturability strategies, and serving as the top-level tapeout owner. The engineer will also contribute to photonic component libraries, guide wafer- and chip-level characterization, and maintain technical relationships with foundry partners on PDKs and process capabilities. Voyant works from its Midtown Manhattan lab and office. The work is hands-on and primarily in person, with schedules that are not rigidly 9-to-5 and may accommodate early or late customer calls across time zones. The company describes its environment as high-trust and high-accountability, with meaningful ownership and varied responsibilities. Catered lunch is provided daily at headquarters.

Requirements

Ph.D. in Electrical Engineering, Applied Physics, Photonics, or a related field, with 5+ years of relevant industry experience.
7+ years of hands-on experience in silicon photonic integrated circuit design, including electromagnetic simulation, active and passive component optimization, and top-level chip layout and floorplanning.
Proven track record taking complex silicon photonics designs through full foundry tapeouts (DRC/LVS) and successful silicon validation and characterization.
Deep expertise in photonic device physics, optical waveguide theory, silicon and silicon nitride fabrication processes, and design-for-manufacturability principles.
Proficiency with industry-standard simulation and layout tools such as Ansys Lumerical, Tidy3D, COMSOL, KLayout, and gdsfactory.
Experience with optical characterization techniques, data analysis in Python or MATLAB, and translating lab measurements into PDK and circuit design updates.
Strong technical leadership capability and excellent communication skills.
Demonstrated ability to collaborate across multidisciplinary teams, including packaging, EIC, systems, and test.

Nice To Haves

Track record designing advanced silicon photonic switches, high-speed optical phase shifters, or ultra-low-loss passive components such as MMIs, mode converters, and polarization splitters/rotators.
Hands-on experience with silicon nitride integration, multi-layer photonic routing architectures, or heterogeneous integration such as III-V on silicon or thin-film lithium niobate.
Deep domain expertise in wideband photonic device performance spanning C-band and O-band telecom/datacom wavelengths.
Strong scripting and automation capabilities in Python or MATLAB for component layout generation, automated simulation sweeps, and high-volume data analysis.
Experience with automated wafer-level testing setups, process variation extraction, and statistical yield modeling for PIC commercialization.

Responsibilities

Lead system-level architecture and design of large-scale silicon photonic integrated circuits, integrating hundreds to thousands of active and passive photonic devices.
Define chip-level optical architectures, link budgets, and performance trade-offs across insertion loss, crosstalk, bandwidth, power consumption, and thermal management.
Drive top-level chip integration, floorplanning, optical routing, and design-for-manufacturability strategies for high-yield silicon photonics tapeouts.
Contribute to photonic component library development.
Serve as top-level tapeout owner, managing design verification (DRC/LVS) and foundry tapeout execution.
Provide technical leadership across multidisciplinary teams, collaborating with component designers, packaging engineers, EIC designers, and system software engineers.
Guide wafer- and chip-level characterization strategies to evaluate full PIC performance against system-level requirements and drive iterative design updates.
Establish and maintain technical relationships with foundry partners to evaluate next-generation PDKs and platform capabilities.