Circuit Design Engineer

Intel•Folsom, CA

9h•Onsite

About The Position

As a Circuit Design Engineer, you will design and optimize digital circuits for custom blocks such as SRAM, register files, memory compilers, and caches. You will perform schematic entry, simulation, and functionality verification to ensure designs meet power, performance, and area goals. Your work will contribute to high-performance solutions for Intel’s data center technologies as part of the Data Center Group (DCG), which develops technology for data centers and advanced computing. The role also involves creating block-level DFT models, developing memory test tools, improving design flows and methodologies, and characterizing memory instances and memory compilers. You will collaborate with architecture, layout, and cross-functional teams to optimize performance, power, area, and yield, and analyze and resolve circuit issues to reduce leakage, improve performance, and enhance circuit robustness. The position is based onsite in Folsom, California. It is listed as a college-graduate role with Shift 1. The annual US salary range is $105,650–$149,150; individual compensation depends on location and job-related factors. Intel describes its compensation package as including competitive pay, stock bonuses, and health, retirement, and vacation benefits.

Requirements

Bachelor’s degree in Electrical or Computer Engineering or a relevant field, with at least 1 year of educational or work experience; alternatively, a master’s degree in the same field with at least 3 months of educational experience.
Experience with circuit simulation tools and methodologies.
Experience with digital circuit design, schematic entry, and verification processes.

Nice To Haves

Familiarity with designing circuits for power, performance, area, and yield optimization.
Understanding of DFT models and memory characterization techniques.

Responsibilities

Design and optimize digital circuits for custom blocks, including SRAM, register files, memory compilers, and caches.
Perform circuit design, schematic entry, simulation, and functionality verification for major blocks.
Create block-level DFT models, develop memory test tools, and enhance design flows and methodologies.
Collaborate with architecture, layout, and cross-functional teams to optimize circuit performance, power, area, and yield.
Analyze and resolve circuit design issues, reducing leakage, optimizing performance, and enhancing circuit robustness.
Characterize memory instances and memory compilers to ensure designs meet specified goals.