Circuit Design Engineer

Intel Corporation•Folsom, CA

21h•$105,650 - $149,150•Onsite

About The Position

As a Circuit Design Engineer in Intel’s Data Center Group, you will design and optimize digital circuits for custom blocks such as SRAM, register files, memory compilers, and caches. The work includes schematic entry, simulation, and functionality verification to ensure designs meet power, performance, and area goals. Your contributions will support high-performance solutions for Intel data center technologies. You will work with architecture, layout, and cross-functional teams to improve circuit performance, power, area, and yield. The role also involves creating block-level DFT models, developing memory test tools, improving design flows and methodologies, resolving circuit design issues, and characterizing memory instances and compilers. This is an on-site, early-career position based in Folsom, California. Intel lists an annual U.S. salary range of $105,650 to $149,150, with compensation determined in part by location, skills, experience, education, and training.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a relevant field, with at least 1 year of educational or work experience; or a master’s degree in the same field with at least 3 months of educational experience.
Experience with circuit simulation tools and methodologies.
Experience with digital circuit design, schematic entry, and verification processes.

Nice To Haves

Familiarity with designing circuits for power, performance, area, and yield optimization.
Understanding of DFT models and memory characterization techniques.
Curiosity, learning agility, and willingness to seek feedback and apply new knowledge.
Analytical problem-solving, creativity, and openness to innovative approaches.
Attention to detail and commitment to accurate, high-quality work.
Initiative, ownership, and follow-through on commitments.
Collaboration and teamwork with diverse teams, including sharing knowledge and contributing to an inclusive environment.
Clear communication of technical concepts and active participation in discussions and reviews.
Adaptability and resilience in a fast-paced environment.

Responsibilities

Design and optimize digital circuits for custom blocks, including SRAM, register files, memory compilers, and caches.
Perform circuit design, schematic entry, simulation, and functionality verification for major blocks.
Create block-level DFT models, develop memory test tools, and enhance design flows and methodologies.
Collaborate with architecture, layout, and cross-functional teams to optimize circuit performance, power, area, and yield.
Analyze and resolve circuit design issues, reduce leakage, optimize performance, and improve circuit robustness.
Characterize memory instances and memory compilers to ensure designs meet specified quality and design goals.