Principal Physical Verification Engineer

Broadcom • San Jose, CA

1d • $143,800 - $230,000 • Onsite

About The Position

Broadcom’s ASIC Products Division is seeking a Physical Verification PD Engineer to work on advanced-node ASIC products, including PCIe Switch Products serving AI and machine-learning ecosystems and Enterprise Products. The role focuses on foundry rules, design for manufacturability, and silicon tape-out and RTO tape-out. The position is based at Broadcom’s San Jose, California site and requires in-person work; remote work is not allowed.

The engineer will execute chip-level physical verification and resolve issues, establish design rule manual (DRM) runsets and tool flows for advanced nodes, and manage rules related to top-level floorplanning, I/O, and bump planning. The role also provides technical direction on verification methodologies and develops best-practice guidelines for physical-verification flows and runtime optimization.

The annual base salary range is USD 143,800 to USD 230,000. The position is eligible for a discretionary annual bonus and new-hire and annual equity awards. Benefits include medical, dental, and vision plans; 401(k) participation with company matching; an employee stock purchase program; an employee assistance program; company-paid holidays; paid sick leave and vacation; and applicable paid family leave and other leaves of absence.

Requirements

• Bachelor’s degree in Electrical Engineering or Electronics Engineering.
• 12+ years of relevant experience.
• In-person work at the San Jose site; remote work is not allowed.
• Excellent verbal and written communication skills.

Nice To Haves

• Hands-on experience running physical verification, including LVS, DRC, ERC, and PERC.
• Experience with EDA tools and flows such as ICV, Calibre, and Pegasus.
• Rule-deck coding experience in ICV, Calibre, or Pegasus.
• Experience resolving chip-level DRC/LVS/EMIR issues for advanced nodes and experience with tape-out.
• Experience with scripting languages such as Python, Tcl, or Perl.
• In-depth knowledge of foundry rules and DFM, and experience in silicon tape-out and RTO tape-out.

Responsibilities

• Execute chip-level physical verification and resolve related issues.
• Set up design rule manual (DRM) runsets for advanced nodes and establish tool flows.
• Manage and guide rules related to top-level floorplanning, I/O, and bump planning.
• Resolve physical-design issues related to chip integration and assembly.
• Provide technical direction on verification methodologies, including DRC, LVS, ERC, and PERC.
• Develop best-practice guidelines for physical-verification flows and runtime optimization.
• Analyze ESD, latch-up, floating-gate, and power-domain-isolation vulnerabilities through ERC/PERC.
• Manage automated dummy metal, poly, and diffusion fill strategies to satisfy local and global density rules.
• Implement design-for-manufacturability fixes, including critical-area analysis, via doubling, and edge-displacement rules.
• Collaborate with physical design (P&R) teams to resolve critical top-level integration bottlenecks.

Benefits

• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.
• Discretionary annual bonus.
• Competitive new-hire equity grant and annual equity awards.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal