Principal Physical Verification Engineer

Celero Communications•Irvine, CA

About The Position

The Principal Physical Verification Engineer leads full-chip and block-level physical verification, owning verification execution plans and schedules and driving quality, milestones, and tapeout readiness. The role runs and analyzes DRC/ERC/LUP/PERC results, supports clean analog IP delivery, and assembles flows for block- and chip-level physical verification. It works across analog, block, and chip teams to support clean floorplans, provide early guidance on corner-case requirements, influence floorplan constraints, hierarchy, and implementation strategy, and participate in tapeout readiness reviews.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or a related field.
7+ years of experience with full-chip verification.
Hands-on experience with a physical verification tool such as ICV or Calibre.
Ability to assemble a flow to support block- and chip-level physical verification.
Strong expertise in floorplanning to avoid DRC/LVS issues.
Understanding of advanced TSMC DRC rules.

Nice To Haves

Experience with advanced technology nodes such as 7nm, 5nm, or 3nm.
Automation skills using Tcl, Python, or shell scripting.

Responsibilities

Lead full-chip physical verification efforts and conduct full-chip and block-level physical verification checks.
Own full-chip verification and develop execution plans and schedules.
Drive accountability for quality, milestones, and tapeout readiness.
Run and analyze DRC/ERC/LUP/PERC results.
Work with the internal analog team to ensure clean IP delivery.
Collaborate with analog, block, and chip top owners to support clean floorplans.
Provide early guidance on corner-case requirements.
Influence floorplan constraints, hierarchy, and implementation strategy.
Participate in tapeout readiness reviews.
Assemble flows that support block- and chip-level physical verification.
Provide guidance to the analog IP team to allow for clean integration.