Principal Physical Verification Engineer

Broadcom • San Jose, CA

1d • $143,800 - $230,000 • Onsite

About The Position

Broadcom is seeking a Physical Verification PD Engineer to join its ASIC Products Division in San Jose, California. The role supports advanced-node ASIC products for artificial intelligence, machine learning, PCIe switch, and enterprise applications. It requires in-depth knowledge of foundry rules and design for manufacturability, along with experience in silicon tape-out and RTO tape-out. The engineer will execute chip-level physical verification, resolve issues, contribute to advanced-node verification flows, and provide technical direction on verification methodologies. This position must be performed in person at the San Jose site; remote work is not allowed.

Requirements

• Bachelor’s degree in Electrical Engineering or Electronics Engineering.
• At least 12 years of relevant experience.
• Must work in person at the San Jose site; remote work is not allowed.

Nice To Haves

• Hands-on experience running physical verification, including LVS, DRC, ERC, and PERC.
• Experience with EDA tools and flows such as ICV, Calibre, and Pegasus.
• Rule-deck coding experience in ICV, Calibre, or Pegasus.
• Experience resolving chip-level DRC, LVS, and EMIR issues for advanced nodes, and tape-out experience.
• Experience analyzing ESD, latch-up, floating gates, and power-domain isolation vulnerabilities through ERC/PERC.
• Experience managing automated dummy metal, poly, and diffusion filling strategies to meet local and global density rules.
• Experience implementing DFM fixes, including critical area analysis, via-doubling, and edge-displacement rules.
• Experience collaborating with physical design (P&R) teams to resolve critical top-level integration bottlenecks.
• Experience with scripting languages such as Python, Tcl, or Perl.
• Excellent verbal and written communication skills.

Responsibilities

• Execute chip-level physical verification and resolve related issues.
• Set up DRM runsets for advanced nodes and tool flows.
• Manage and guide rules related to top-level floorplanning, I/O, and bump planning.
• Resolve physical design issues related to chip integration and assembly.
• Provide technical direction on verification methodologies, including DRC, LVS, ERC, and PERC.
• Develop best-practice guidelines for physical verification flows and runtime optimizations.

Benefits

• Discretionary annual bonus.
• Competitive new-hire equity grant and opportunity for annual equity awards.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal