Principal Physical Design Engineer

Celero Communications • San Jose, CA

5d

About The Position

The Principal Physical Design Engineer owns physical implementation from RTL to GDSII for SoCs or complex digital blocks. The role optimizes chip performance through floor planning, bump planning, power grid design, and clock tree synthesis; resolves timing, congestion, and EM/IR issues with frontend designers; and performs signoff and physical verification. The engineer also develops automation and improves flow robustness, while partnering with architecture, logic design, and analog design teams to ensure tapeout readiness.

Requirements

• 7+ to 15+ years of relevant ASIC physical design experience, depending on degree level.
• Deep tapeout experience in advanced technology nodes such as 7nm, 5nm, or 3nm.
• Advanced proficiency with industry-standard EDA tools, including Cadence tools such as Innovus, Tempus, Voltus, Pegasus, and Calibre.
• Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Responsibilities

• Own RTL-to-GDSII physical implementation of SoCs or complex digital blocks.
• Manage floor planning, bump planning, power grid design, and clock tree synthesis to optimize chip performance.
• Resolve timing, congestion, and EM/IR issues with frontend designers.
• Run Static Timing Analysis (STA) and physical verification; fix DRC and LVS violations.
• Drive automation and improve flow robustness using Tcl, Python, or Perl.
• Partner with architects, logic designers, and analog design teams for tapeout readiness.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed