Principal Physical Design Engineer

Celero Communications • Irvine, CA

5d

About The Position

The Principal Physical Design Engineer owns the physical implementation of SoCs or complex digital blocks from RTL to GDSII. The role optimizes chip performance through floor-planning, bump planning, power grid design, and clock tree synthesis, and works with frontend designers to resolve timing, congestion, and EM/IR issues. It also covers static timing analysis, physical verification, and correction of DRC and LVS violations. The engineer drives automation and improves flow robustness using scripting, and partners with architects, logic designers, and analog design teams to prepare designs for tapeout.

Requirements

• 7+ to 15+ years of relevant ASIC physical design experience, depending on degree level.
• Deep tapeout experience in advanced technology nodes such as 7nm, 5nm, or 3nm.
• Advanced proficiency with industry-standard EDA tools, including tools from Cadence such as Innovus, Tempus, Voltus, and Pegasus, as well as Calibre.
• Expertise in physically aware synthesis, power domain analysis, and electromigration/IR-drop cleanup.

Responsibilities

• Own RTL-to-GDSII physical implementation of SoCs or complex digital blocks.
• Manage floor-planning, bump planning, power grid design, and clock tree synthesis to optimize chip performance.
• Resolve timing, congestion, and EM/IR issues with frontend designers.
• Run static timing analysis and physical verification.
• Fix design rule checking and layout versus schematic violations.
• Drive automation and improve flow robustness using scripting languages such as Tcl, Python, or Perl.
• Partner with architects, logic designers, and analog design teams for tapeout readiness.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed