Principal Modem PHY IP Design Verification Engineer - Terawave

BLUE ORIGIN•San Diego, CA

9d•$269,175 - $376,844

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. We are seeking a Principal Modem PHY IP Design Verification Engineer to lead and execute verification of advanced modem PHY IP for the Terawave program. This role is responsible for developing robust verification strategies, building scalable verification environments, and ensuring high-quality modem PHY IP delivery for next-generation wireless ASIC platforms. The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems. This engineer will work closely with PHY architects, RTL designers, systems engineers, firmware, FPGA, and validation teams to verify functionality, performance, and integration of modem PHY IP across simulation, emulation, prototyping, and silicon bring-up phases.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
10+ years of experience in digital design verification, ASIC/SoC verification, or modem/baseband verification.
Strong experience with SystemVerilog and modern verification methodologies such as UVM.
Experience developing verification environments for complex DSP, modem, or communications IP.
Familiarity with one or more of the following modem PHY areas: OFDM and/or single-carrier systems, synchronization, channel estimation and equalization, FEC such as LDPC, Polar, Turbo, or BCH, MIMO / beamforming, fixed-point and quantized signal processing.
Experience with scripting and automation using Python, Perl, shell, or similar tools.
Strong debugging and problem-solving skills across RTL, testbench, and model correlation issues.
Ability to work closely with design, architecture, and systems teams in a fast-paced development environment.

Nice To Haves

Master’s degree in Electrical Engineering, Computer Engineering, Signal Processing, Communications, or related field.
Experience verifying modem PHY or baseband IP for: mmWave / sub-THz / Terahertz systems, satellite or space communications, 5G/6G systems, high-throughput wireless backhaul or mesh systems.
Experience with MATLAB, C/C++, or Python-based reference models for algorithm correlation.
Familiarity with assertions, formal verification, lint, CDC, RDC, and low-power verification methodologies.
Experience with emulation, FPGA prototyping, and post-silicon validation/debug.
Knowledge of RF/system impairments and their impact on modem PHY behavior, including phase noise, frequency offset, nonlinearities, and channel effects.
Experience working with external IP vendors or design service partners.
Ability to operate effectively in an ambiguous, fast-moving development environment.

Responsibilities

Develop and execute verification strategy and plans for modem PHY IP and subsystem-level integration.
Build and maintain block-level and subsystem-level verification environments for PHY IP using industry-standard methodologies.
Create testbenches, stimulus, checkers, scoreboards, assertions, and coverage models to verify modem PHY functionality and corner cases.
Verify key PHY IP functions such as: modulation and demodulation, timing and frequency synchronization, channel estimation and equalization, MIMO / beamforming support, FEC integration, control, configuration, and status interfaces, impairment handling and recovery behavior.
Collaborate with PHY algorithm and architecture teams to correlate RTL behavior against floating-point, fixed-point, or bit-accurate reference models.
Define and track functional, code, assertion, and scenario coverage to ensure verification completeness.
Develop constrained-random and directed test strategies for feature, stress, and corner-case validation.
Identify, debug, and root-cause design and integration issues in collaboration with RTL and architecture teams.
Support verification of performance-sensitive designs with attention to throughput, latency, buffering, and protocol timing behavior.
Contribute to regression automation, CI flows, and verification infrastructure improvements.
Support subsystem integration, FPGA prototyping, emulation, and post-silicon debug as needed.
Document verification plans, test results, coverage status, and quality metrics.
Work effectively with internal engineering teams and external design service partners to drive verification closure.