Principal Hardware Design Engineer (Data Center)
About The Position
Qualcomm Technologies’ Central Hardware Systems hardware design team develops hardware systems and printed circuit boards across strategic platforms, including data center, server, connectivity, compute, and R&D. The Principal Hardware Design Engineer leads development of embedded hardware for Qualcomm SoC-based data center platforms, ranging from test and R&D platforms to accelerator and CPU cards, multi-card server systems, and rack-level designs. These platforms support production, reference designs, verification and validation, software and firmware development, and SoC testing. The role covers high-power, high-density systems with high-speed interconnects, including LPDDR, HBM and DDR5 memory; PCIe Gen5/Gen6 and CXL; 400G/800G Ethernet fabrics; 112G+ SerDes; high-current multi-phase power delivery; advanced thermal solutions such as direct liquid cooling; and board management and security subsystems. The engineer works with server ODMs and Qualcomm’s SoC, software, and systems teams to deliver reliable, scalable production platforms. This position provides technical and project leadership throughout the hardware lifecycle, from architecture and requirements through design, validation, bring-up, system integration, and production. It also drives design methodologies, analysis and validation practices, cross-functional problem solving, ODM handoff, innovation, and technical mentorship. The position is full-time and onsite in San Diego, California.
Requirements
- Bachelor’s or master’s degree in Electrical Engineering, Computer Science, or a related field; the additional minimum qualifications also specify a bachelor’s degree in Engineering or a related field with 8+ years of hardware engineering experience, a master’s degree with 7+ years, or a PhD with 6+ years.
- 15+ years of experience in hardware engineering-related work, including areas such as digital or analog circuit design, schematic capture, circuit simulation, power/signal integrity simulation tools, lab/measurement/test equipment, and technical project leadership.
- Technical project leadership across the full hardware development lifecycle.
- Experience using lab measurement and test equipment, including high-bandwidth oscilloscopes, VNA/TDR, BERT, and power analyzers.
Nice To Haves
- Hands-on experience delivering AI/ML accelerator, GPU, or high-performance compute cards or servers into data center production.
- Experience with PCIe Gen5/Gen6, CXL, 112G/224G PAM4 SerDes, and high-speed Ethernet (400G/800G).
- Expertise in high-current power delivery (500A+ rails), 48V power architectures, and VR design and validation.
- Experience with HBM, LPDDR5/5X, or DDR5 memory subsystem design.
- Familiarity with OCP specifications (OAM, OCP NIC 3.0, DC-MHS, ORv3) and rack-scale system design.
Responsibilities
- Lead hardware projects and design teams from architecture and requirements through design, validation, bring-up, system integration, and production.
- Develop and drive hardware design methodologies, design rules, implementation flows, validation strategies, DFx, RAS practices, and engineering best practices for data center deployment.
- Lead system-level design optimization and resolve complex electrical, optical, mechanical, compatibility, compliance, manufacturing, and cost issues.
- Provide technical leadership for signal integrity, power integrity, feasibility, characterization, and hardware validation analysis.
- Define platform architecture for performance, power, density, and total cost of ownership, including memory topology, host and accelerator interconnects, networking, and power and thermal budgets.
- Lead design of high-current, low-voltage, multi-phase power delivery networks and drive power integrity analysis from board through package to die.
- Lead signal integrity work on 112G/224G SerDes, PCIe Gen5/Gen6, CXL, Ethernet, and high-speed memory interfaces, including channel modeling, pre- and post-layout simulation, and correlation with lab measurements.
- Lead hardware bring-up, characterization, and debugging of new AI SoCs and platforms; support SoC testing and post-silicon validation; collaborate with software and firmware teams to optimize inference workloads.
- Collaborate with IC design, software, systems, packaging, ML systems, test, Customer Engineering, product management, supply chain, manufacturing, and operations teams.
- Coordinate design handoff to server ODMs and contract manufacturers and support ODM design, NPI, and volume production.
- Serve as a technical authority and mentor by conducting design reviews and providing technical direction and guidance across engineering teams and projects.
- Track industry standards, including OCP, PCI-SIG, CXL Consortium, UEC/UALink, and DMTF, and apply expertise to drive innovation, intellectual property, process improvement, and product roadmaps.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for the annual bonus).
- Competitive benefits package designed to support employees at work, at home, and at play.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
