Principal Engineer (8009)

TSMC•San Jose, CA

1d•$218,899 - $220,000

About The Position

Apply SoC (System on Chip) and high-speed, low-power VLSI design principles to participate in chip physical design and implementation using TSMC’s advanced processing technology. Work includes block-level floor planning, clock tree synthesis, place and route, RC extraction, static timing analysis and timing closure, IR/EM analysis and fixes, DRC/LVS/ERC clean-up, and tape-out sign-off. Use standard EDA tools and Perl/TCL programming. Provide onsite customer support. The role is based at TSMC Technology, Inc. in San Jose, California, and at various unanticipated locations. Employment is contingent on obtaining any U.S. Government export license or other approval that may be required for access to technical data subject to export control regulations.

Requirements

Bachelor’s degree or foreign equivalent in Electrical or Electronic Engineering.
Five years of experience in a related position.
Experience in full-cycle physical design implementations and PPA analysis of CPU blocks in lower technologies, including N7/N5 and lower.
Proficiency in Verilog and VHDL hardware description languages.
Knowledge of Tcl and Perl scripting languages.
Knowledge of electrical and electronic engineering principles, including Circuit Theory, Solid State Devices and Circuit, Digital Electronic Circuits, VLSI Circuits and Systems, and Electronic Design Automation.

Responsibilities

Participate in chip physical design and implementation for TSMC’s advanced processing technology.
Perform block-level floor planning, clock tree synthesis, place and route, RC extraction, static timing analysis, and timing closure.
Conduct IR/EM analysis and fixes.
Perform DRC/LVS/ERC clean-up and tape-out sign-off.
Use standard EDA tools and Perl/TCL programming.
Provide customer onsite support.