Principal Engineer (8009)

TSMC•West Covina, CA

1d•$218,899 - $220,000•Onsite

About The Position

The Principal Engineer applies SoC and high-speed, low-power VLSI design principles to chip physical design and implementation for TSMC’s advanced process technologies. The work includes block-level floor planning, clock tree synthesis, place and route, RC extraction, static timing analysis and timing closure, IR/EM analysis and fixes, DRC/LVS/ERC cleanup, and tape-out sign-off. The role uses standard EDA tools and Perl/TCL programming and provides onsite customer support. The work site is TSMC Technology, Inc., 2851 Junction Avenue, San Jose, California 95134, and various unanticipated locations.

Requirements

Bachelor’s degree or foreign equivalent in Electrical or Electronic Engineering.
Five years of experience in a related position.
Experience in full-cycle physical design implementations and PPA analysis of CPU blocks in lower technologies, including N7/N5 and lower.
Proficiency in Verilog and VHDL hardware description languages.
Knowledge of TCL and Perl scripting languages.
Knowledge of electrical and electronic engineering principles, including Circuit Theory, Solid State Devices and Circuit, Digital Electronic Circuits, VLSI Circuits and Systems, and Electronic Design Automation.

Responsibilities

Participate in chip physical design and implementation for advanced processing technology.
Perform block-level floor planning, clock tree synthesis, place and route, RC extraction, static timing analysis, and timing closure.
Perform IR/EM analysis and fixes, including voltage-drop and electro-migration analysis.
Complete DRC/LVS/ERC cleanup and tape-out sign-off.
Use standard EDA tools and Perl/TCL programming.
Provide onsite customer support.