Apply principles of System on Chip (SoC) and high-speed, low-power VLSI design to participate in chip physical design and implementation for TSMC’s advanced processing technology. Work includes block-level floor planning, clock tree synthesis, place and route, RC extraction, static timing analysis (STA) and timing closure, IR/EM analysis and fixes, DRC/LVS/ERC cleanup, and tape-out signoff, using standard EDA tools and Perl/TCL programming. The position also provides customer onsite support. The work site is TSMC Technology, Inc., 2851 Junction Avenue, San Jose, CA 95134, and various unanticipated locations. The posted salary range is $218,899 to $220,000 per year. TSMC’s total compensation package includes market-competitive pay, allowances, bonuses, comprehensive benefits, and development opportunities. Employment is contingent on obtaining any export license or other U.S. Government approval that may be required for access to technical data subject to export control regulations.
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Job Type
Full-time
Career Level
Principal