Principal Engineer, SOC IP Systems & Lifecycle Management

Astera Labs • San Jose, CA

20h

About The Position

Astera Labs is seeking a Principal Engineer to lead the strategic development of their AI-powered IP Lifecycle Management and IP Quality Assurance Platform. This role is crucial for ensuring all internal and external Intellectual Property (IP) is SOC-ready, preventing integration issues that could delay product releases. The candidate will architect a scalable, user-friendly system that forms the foundation of Astera Labs' "AI-first" IP ecosystem. Responsibilities include auditing and qualifying various types of IP, ensuring the platform scales to cover SOC QA and tape-out sign-off requirements. The successful candidate will possess expertise in running EDA tools, interpreting results, identifying false positives, and resolving root-cause errors by collaborating with vendors or internal IP teams. The role emphasizes ensuring IP deliveries are integrable, timing-clean, and manufacturable, thereby avoiding late-stage SOC breaks due to inconsistent IP views or structural violations. IPQA will encompass the entire design flow, from architecture coherence and PPA evaluation to Front-End integration, SDC, RDC, DFT, PD, PDV, Packaging, ESD, Waivers, and IP-XACT, scaling from technology foundations to SOC quality.

Requirements

• Mastery of the full sign-off suite: PrimeTime, Fusion Compiler, Genus, Calibre, Innovus, IC Compiler, SpyGlass, Tessent, Liberate (/MX), PrimeSim.
• Cross-Tool Consistency expertise is a must.
• Expert in Tcl for tool manipulation and Python for building AI-wrapper layers.
• Familiarity with SystemVerilog.
• Deep understanding of FinFET/Gate-All-Around (GAA) properties, Electromigration (EM), and ESD rules.
• Deep knowledge of Liberty modeling and LEF/DEF physical formats.
• A "Detective" mindset with the ability to look past a "green" or “red” report to find false errors and rootcause real ones.
• Ability to work with design teams and IP vendors to solve issues in a timely manner.

Responsibilities

• Architect and lead the integration of agentic AI workflows into the IPLM and IPQA platform to automate IP Management, root-cause analysis of false pass scenarios and self-heal real issues.
• Verify IP compliance with high-speed and high-bandwidth interface standards for heterogeneous integration (Chiplet Readiness).
• Architect automated audits for logical-to-physical consistency across RTL, Liberty, LEF, GDSII, and CDL views, focusing on pin-naming, bus-integrity, and functionality (Cross-View Consistency).
• Perform independent LVS, DRC, and Antenna signoffs using native runsets for 5nm/3nm and beyond nodes (Physical & Sign-off Audits).
• Validate DFT requirements, including scan-chain integrity, MBIST handshakes, and fault-coverage transparency (Structural & DFT Verification).
• Audit Power Domain (UPF/CPF) consistency and conduct deep-dive Liberty (.lib) audits to identify missing timing arcs or non-monotonic lookup tables. Audit IR-drop/EM (Electromigration) reports to ensure the IP won't cause localized power grid failures (Power & Timing Integrity).
• Develop rigorous, automated Waiver Audit Protocol to ensure that provider-cleared violations do not violate Astera Labs' internal sign-off deck requirements (Waiver Management).
• Track and check lessons learned from release to release, generation to generation.
• Ensure releases are complete, patches are integrated, constraints are updated, and documentation reflects updates including PPA impact.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: No Education Listed
• Number of Employees: 101-250 employees