Principal Engineer-Design (SoC Integration and RTL/IP)

Microchip•Chandler, AZ

About The Position

The dsPIC microcontroller group is seeking an experienced SoC Integration, RTL/IP Design, and FPGA Engineer to lead SoC integration, RTL development, IP design, and FPGA prototyping activities. The role works closely with architecture, verification, and physical design teams to deliver high-quality hardware solutions. The engineer will independently drive SoC integration, IP design, and FPGA prototyping while providing technical leadership and ensuring robust, reusable hardware designs. Expected deliverables include integrated SoC/subsystem RTL and reusable IP modules, FPGA implementation and validation results, and design quality reports and integration documentation. Travel is listed as 0%–25%.

Requirements

Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field, with 10+ years of experience in ASIC/SoC design, RTL development, FPGA, or SoC integration.
Strong knowledge of SystemVerilog and AMBA AXI/AHB/APB protocols.
Experience with SoC integration, IP development, clock/reset architecture, and memory mapping.
Hands-on experience with Vivado or Quartus, synthesis, STA, and timing closure.
Familiarity with simulation tools such as QuestaSim, VCS, or Xcelium.
Knowledge of CDC/RDC, RTL lint, and Python/Tcl scripting.

Nice To Haves

Experience with ARM- or RISC-V-based SoCs, Ethernet, USB, SPI, I2C, and UART interfaces.
Knowledge of low-power design, DFT integration, and formal-based verification.
Experience with FPGA synthesis, place and route, timing closure, constraint development, and FPGA-based validation.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related field.

Responsibilities

Perform top-level and subsystem integration of processors, memories, peripherals, and custom IPs.
Integrate IPs using proprietary bus interfaces and AMBA AXI, AHB, and APB protocols.
Handle clock/reset integration, interrupt routing, address mapping, and pad/pin connectivity.
Resolve chip-level lint, synthesis, and timing issues; perform CDC/RDC analysis and implement relevant fixes.
Own post-silicon debug and ECO revisions of chip RTL and IP.
Develop synthesizable RTL using SystemVerilog.
Design reusable peripherals, memory/ADC/PWM controllers, wrappers, and power management modules.
Perform RTL reviews, support synthesis, optimize timing, and debug designs.
Maintain, enhance, and manage older IP.
Collaborate with architecture, verification, DFT, physical design, firmware, and system teams.
Lead design reviews, mentor junior engineers, and drive technical improvements.
Help make key decisions related to IP and product definition and implementation.
Deliver integrated SoC/subsystem RTL and reusable IP modules, FPGA implementation and validation results, and design quality reports and integration documentation.