Principal Engineer-Design (SoC Integration and RTL/IP)

Microchip Technology Inc.•Chandler, AZ

About The Position

Microchip Technology’s dsPIC microcontroller group is seeking an experienced SoC integration, RTL/IP design, and FPGA engineer. The role leads SoC integration, RTL development, IP design, and FPGA prototyping, working closely with architecture, verification, and physical design teams to deliver high-quality hardware solutions. The engineer independently drives SoC integration, IP design, and FPGA prototyping while providing technical leadership and ensuring robust, reusable hardware designs. Expected deliverables include integrated SoC or subsystem RTL and reusable IP modules, FPGA implementation and validation results, and design quality reports and integration documentation.

Requirements

Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field, with 10+ years of experience in ASIC/SoC design, RTL development, FPGA, or SoC integration.
Strong knowledge of SystemVerilog and AMBA AXI, AHB, and APB protocols.
Experience with SoC integration, IP development, clock/reset architecture, and memory mapping.
Hands-on experience with Vivado or Quartus, synthesis, static timing analysis (STA), and timing closure.
Familiarity with simulation tools such as QuestaSim, VCS, or Xcelium.
Knowledge of CDC/RDC, RTL lint, and Python or Tcl scripting.

Nice To Haves

Experience with ARM- or RISC-V-based SoCs and Ethernet, USB, SPI, I2C, and UART interfaces.
Knowledge of low-power design, DFT integration, and formal-based verification.
Experience with FPGA synthesis, place and route, timing closure, constraint development, and FPGA-based validation.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related field.

Responsibilities

Perform top-level and subsystem integration of processors, memories, peripherals, and custom IPs.
Integrate IPs using proprietary bus interfaces and AMBA AXI, AHB, and APB protocols.
Handle clock and reset integration, interrupt routing, address mapping, and pad and pin connectivity.
Resolve chip-level lint, synthesis, and timing issues; perform CDC and RDC analysis and implement relevant fixes.
Own post-silicon debug and chip ECO revisions.
Develop synthesizable RTL using SystemVerilog.
Design reusable peripherals, memory, ADC, and PWM controllers, wrappers, and power management modules.
Resolve lint, synthesis, timing, and CDC/RDC issues.
Perform RTL reviews, support synthesis, optimize timing, and debug designs.
Maintain, enhance, and manage older IP.
Collaborate with architecture, verification, DFT, physical design, firmware, and system teams.
Lead design reviews, mentor junior engineers, and drive technical improvements.
Contribute to key decisions regarding IP and product definition and implementation.
Produce integrated SoC or subsystem RTL, reusable IP modules, FPGA implementation and validation results, design quality reports, and integration documentation.