Principal Design Engineer

Micron•San Jose, CA

About The Position

Micron Technology’s Non-Volatile Engineering Group develops NAND memory products, and is embedding AI across its design flow. As a Principal Design Engineer on the NAND datapath team, you will lead the architecture, design, and verification of the internal datapath between the page buffer and IO, including wave-pipelined buses, flop-to-flop timing, FIFOs, dataline sensing, column repair, and clocking. You will use AI daily to accelerate design, timing closure, and verification; help bring an STA-based semi-custom methodology into a simulation-only flow; and set technical direction as a recognized leader. The role includes leading semi-custom methodology development, physical co-design with layout, cross-functional interface definition, silicon debug, and mentoring engineers. Micron encourages daily AI use for RTL generation, scripting, and timing and waveform analysis, along with developing AI-processable specifications and agents to automate timing, Monte Carlo, and repair-coverage checks. This is a full-time position. The estimated US base salary range is $181,000 to $308,000 per year. Additional compensation may include benefits, bonuses, and equity. Micron offers medical, dental, and vision plans, income-protection programs, paid family leave, paid time off, and paid holidays.

Requirements

BS or MS in electrical engineering or a related field.
At least 8 years of experience in memory datapath, SRAM, or high-speed custom design.
Deep expertise in flop-to-flop and wave-pipelined timing closure, including setup/hold, skew, minimum/maximum delay, and PVT margin.
Experience in sense amplifier, dataline, or SRAM read/write design, including Monte Carlo/high-sigma verification.
Proven collaboration with layout on floorplanning, extraction, and post-layout timing correlation.
Daily hands-on AI use, with concrete examples of AI-based workflows—such as prompts, scripts, or agents—that improved productivity or design outcomes.

Nice To Haves

NAND, DRAM, or SRAM periphery experience, including page buffers, column decoders, global data buses, or array-to-IO pipelines.
Memory repair and redundancy design experience, including understanding the impact on yield, area, timing, and test time.
Experience with timing-adjustment techniques such as delay trims, DLL/DCC, or training, and with aging effects such as NBTI/HCI.
Experience building AI agents, LLM/RAG pipelines, or ML models for IC design, verification, or debug.
Knowledge of CMOS device physics, mismatch modeling (BSIM), and low-power techniques such as clock/power gating and leakage.
Solid understanding of STA and semi-custom flows that combine custom and standard-cell logic.

Responsibilities

Define, design, and verify internal datapath blocks, including page-buffer-to-IO data buses, wave pipelines, FIFOs, SER/DES front ends, and datapath clocking, to meet bandwidth, timing, and power targets.
Architect and close wave-pipelined and flop-to-flop paths, addressing setup and hold, skew and jitter budgets, PVT delay tracking, and delay trims across PVT and aging.
Design dataline sense amplifiers and precharge/latch sensing, accounting for offset, Monte Carlo/high-sigma margin, coupling, and IR drop.
Design column repair, fuse/repair storage, and redundancy muxing without bandwidth or timing penalties; verify repair configurations with test, PE, and FW.
Use AI daily for RTL generation, scripting, and timing and waveform analysis.
Develop specifications and checklists that AI can process, and build agents to automate timing, Monte Carlo, and repair-coverage checks.
Lead the transition from SPICE-only closure to a semi-custom flow using characterized custom cells, SDC/STA sign-off, STA-to-SPICE correlation, and synthesis/APR/ECO flows.
Drive floorplanning, bus routing, and RC-aware delay matching with layout, and correlate post-layout timing.
Champion AI adoption and standard processes, define interface specifications with multifunctional teams, support silicon debug, and mentor engineers.