Principal D2D SerDes & Analog Layout Design Engineer

Microsoft•Mountain View, CA

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) builds the infrastructure and foundational technologies supporting Azure, Microsoft 365, Teams, Xbox, and next-generation AI platforms. The Semi & Custom IP team develops advanced analog and mixed-signal IP, including die-to-die (D2D) SerDes interfaces, for AI accelerators, cloud infrastructure, and custom silicon platforms. The Principal D2D SerDes & Analog Layout Design Engineer provides technical leadership for matching-critical analog layout and D2D SerDes physical implementation. The role establishes layout strategy and methodology, leads complex subsystem execution across internal and external contributors, influences architecture and integration decisions, and drives production-ready IP from early feasibility through tapeout and silicon learning. It offers broad organizational impact and the opportunity to shape long-term D2D and advanced-node layout capabilities for strategic silicon programs.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or a master's degree in one of these fields and 6+ years of experience; or a bachelor's degree in one of these fields and 8+ years of experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Eligibility to access export-controlled information, with citizenship or qualifying residency/protected status verified using the documentation specified in the posting.

Nice To Haves

8+ years of analog or mixed-signal layout experience, including matching-critical transistor-level layout and complex subsystem integration in advanced process technologies.
Experience leading analog, mixed-signal, SerDes, or D2D IP physical implementation through floorplanning, verification, signoff, tapeout, and integration.
Experience using Cadence Virtuoso and Siemens/Mentor Calibre physical verification tools.
Experience with DRC, LVS, ERC, antenna, extraction-aware layout, EMIR or reliability considerations, and advanced-node physical signoff.
Experience providing technical leadership across multiple layout contributors and influencing circuit design, CAD, package, signal-integrity, physical-design, or SoC integration teams.
Deep experience with high-speed SerDes, D2D interfaces, or comparable high-performance analog/mixed-signal IP, including transmitter, receiver, clocking, bias, equalization, PLL/DLL, or related circuitry.
Expertise in analog matching, symmetry, layout-dependent effects, device orientation, process gradients, coupling, isolation, shielding, return paths, and parasitic optimization.
Experience with D2D standards or implementations such as UCIe, BoW, or proprietary die-to-die links.
Experience defining physical implementation strategy for advanced packaging and chiplet integration, including die-edge planning, bump or micro-bump interfaces, ESD, package escape, power delivery, and signal-integrity constraints.
Experience influencing circuit, interface, floorplan, or package decisions based on implementation feasibility, extraction, EMIR, reliability, and system-level tradeoffs.
Experience leading top-level assembly and verification of analog subsystems developed by multiple engineers, organizations, or external partners.
Experience with EMIR and reliability signoff using Ansys Totem, Cadence Voltus, or equivalent tools.
Experience with Cadence automated place-and-route (APR) flows, including floorplanning, placement, clock or signal routing, physical optimization, and integration of custom analog or mixed-signal IP with digitally implemented logic.
Strong automation and methodology-development skills using Python, SKILL, TCL, Perl, or similar languages.
Experience with FinFET and/or Gate-All-Around technologies and advanced nodes such as 5nm, 3nm, or beyond.
Demonstrated success mentoring senior engineers, establishing technical standards, resolving complex cross-organizational issues, and influencing engineering leadership.
Experience governing technical delivery across geographically distributed teams, contractors, vendors, or design-service partners over multiple milestones or programs.
Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check and requirements for access to export-controlled information.

Responsibilities

Own physical implementation strategy and technical execution for complex D2D SerDes and analog/mixed-signal subsystems in advanced process technologies, from feasibility and architecture definition through tapeout, integration, and silicon learning.
Define top-level D2D analog front-end floorplans and integration strategies, addressing partitioning, hierarchy, die-edge constraints, bump or micro-bump alignment, ESD interfaces, power delivery, sensitive routing, clocking, and package-aware tradeoffs.
Establish matching, isolation, and parasitic-control methods for critical circuits using symmetry, common-centroid placement, interdigitation, device-orientation control, dummy structures, shielding, guard rings, return-path planning, and gradient mitigation.
Lead technical execution across blocks, engineers, and design partners by defining implementation plans, setting quality expectations, conducting design reviews, managing dependencies, and driving milestone and signoff closure.
Influence circuit, PHY, package, signal-integrity, physical-design, ESD, CAD, and SoC integration decisions by translating implementation limits and extracted-layout results into architectural recommendations.
Resolve high-impact layout risks for transmitter, receiver, clocking, bias, equalization, PLL/DLL, and related analog front-end circuitry, including issues spanning blocks and organizational boundaries.
Drive physical verification and production-signoff strategy, including DRC, LVS, ERC, antenna, density, extraction review, EMIR, reliability analysis, layout-dependent effects, waiver judgment, and hierarchical closure.
Define and maintain layout quality criteria, review checklists, release requirements, signoff evidence, and technical acceptance criteria for internally and externally developed D2D and analog IP.
Guide delivery of production-ready IP collateral, including GDS/OASIS, LEF abstracts, integration views, interface documentation, waiver rationale, review records, and signoff packages for SoC and package integration.
Create and scale reusable analog-layout methodologies, templates, automation flows, and productivity solutions using SKILL, TCL, Python, Cadence APR, or similar technologies.
Provide technical direction and mentorship to senior engineers and partner teams, improve review quality, and grow organizational capability in advanced-node analog and D2D layout.
Govern technical execution with contractors, vendors, and geographically distributed design partners, including work partitioning, quality assessment, corrective action, and delivery accountability.
Communicate technical strategy, status, risks, options, and recommendations to engineering and program leadership, and drive alignment on decisions affecting multiple teams or silicon programs.
Identify longer-term technology, methodology, staffing, and enablement needs for future D2D and analog IP generations and translate them into actionable development plans.