Principal ASIC Design Engineer

Micron Technology • San Jose, CA

1d • $186,000 - $407,000 • Onsite

About The Position

Micron's Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A core part of that work is silicon-based validation of novel PHY solutions, and we are growing the team to execute. As the Principal ASIC Design Engineer, you will be the primary digital contributor on a deliberately small, senior team — united around the goal of carrying high-speed interface technologies from architecture to tape-out. The team’s analog and chip-level architecture is anchored by a deeply experienced analog custom design engineer; your role is to be the authoritative digital voice — owning RTL design and micro-architecture of the digital blocks, defining timing constraints, supporting verification, and serving as the key interface between the digital design and the analog and layout specialists who will carry the implementation through to silicon. On a test ASIC of this scope, the front-end digital work is the critical path, with contractor and layout support engaged as bandwidth demands warrant.

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
• 7–12 years of ASIC design experience with at least one complete front-to-back tape-out
• Proficiency in synthesizable SystemVerilog RTL design — linting-clean, well-documented coding practices
• Hands-on experience with logic synthesis (Design Compiler or Genus) and static timing analysis (PrimeTime or Tempus)
• Proficiency with RTL simulation and debug tools (VCS or Xcelium; Verdi or DVE) for block-level self-verification
• Solid understanding of CDC analysis methodologies (SpyGlass, JasperGold CDC, or equivalent)
• Ability to work effectively at the interface between digital design and custom/analog implementation teams — translating design intent into actionable guidance for layout and implementation specialists
• Strong written communication skills — this role produces specifications and documentation, not just code
• Proficiency in leveraging AI tools for productivity across design, debug, and documentation workflows

Nice To Haves

• Experience working within a custom mixed-signal design team — comfortable operating alongside analog designers, layout engineers, and characterization specialists as a collaborative peer
• Hands-on experience with place-and-route (Cadence Innovus or equivalent) and physical verification sign-off (Mentor Calibre) — candidates with full front-to-back implementation experience are strongly encouraged to apply
• Experience with mixed-signal or PHY-adjacent chip implementation — analog/digital partitioning, analog supply isolation, mixed-signal physical integration
• Familiarity with high-speed PHY architectures (SerDes, DDR, or equivalent)
• Familiarity with digital infrastructure for observability and silicon characterization — including PRBS generators, error counters, monitor interfaces, debug registers, and support for first silicon bring-up
• Familiarity with I2C management bus, Eye Monitor control logic, or PRBS-based error counting
• Familiarity with DFT methodologies — scan insertion, ATPG planning, boundary scan
• Experience with GLS flows using Liberty models and SPF parasitics
• Familiarity with formal property verification (JasperGold or VC Formal)
• Prior experience in a small team or startup-like environment

Responsibilities

• Own the micro-architecture and RTL implementation of all digital soft IP blocks — CSR/register file, clocking control logic, management bus interfaces, and control state machines — in synthesizable SystemVerilog.
• Define and document block-level architecture specifications and interface control documents; serve as the authoritative reference for digital design intent.
• Define CDC strategy for digital blocks and ensure clean closure using standard analysis tools.
• Coordinate with the analog design lead on top-level chip integration, analog/digital partitioning, and chip boundary interface definitions.
• Execute logic synthesis (Synopsys Design Compiler or Cadence Genus) and drive optimization toward PPA targets.
• Develop and maintain block-level SDC constraints; execute and close static timing analysis (PrimeTime or Tempus) across required corners and modes.
• Serve as the primary digital interface to the layout and implementation team — providing synthesized netlists, SDC constraints, floorplan guidance, and design intent documentation to enable effective physical implementation.
• Review and provide feedback on floorplan decisions, placement constraints, and timing closure results; partner with layout specialists to resolve implementation issues rooted in RTL or constraints.
• Coordinate with the verification team on scan chain insertion, DFT strategy, and ATPG planning.
• Where bandwidth and experience allow, participate directly in place-and-route and physical verification flows.
• Self-verify RTL through block-level simulation (VCS or Xcelium), waveform debug (Verdi or DVE), and directed testing before engaging the verification team.
• Write SystemVerilog Assertions (SVA) for critical control sequences and protocol compliance.
• Collaborate with the Design Verification Engineer on the block-level verification plan, testbench coverage, and bug resolution.
• Support GLS and timing simulation using released netlists and SPF/parasitics; assist lab bring-up with simulation waveforms and register-level debug.
• Maintain block specifications, SDC rationale, implementation guidance, and ECO history as institutional knowledge for follow-on chip development.

Benefits

• choice of medical, dental and vision plans
• benefit programs that help protect your income if you are unable to work due to illness or injury
• paid family leave
• robust paid-off program
• paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Principal