Power Engineer

Apple•Cupertino, CA

3d•$174,149 - $225,300

About The Position

Apple Inc. is hiring a Power Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The role focuses on reducing CPU power through micro-architecture and circuit ideas, analyzing CPU power across use cases, and optimizing power efficiency across current and future CPU designs. The engineer will work with micro-architects, physical designers, software teams, and platform teams, and will help define and tune power management features. The position is 40 hours per week. The base pay range is $174,149–$225,300 per year, with compensation depending on skills, qualifications, experience, and location. Apple offers eligible employees access to discretionary stock programs, including restricted stock unit awards and an Employee Stock Purchase Plan. Benefits include comprehensive medical and dental coverage, retirement benefits, discounted products, free services, and reimbursement for certain education expenses, including tuition. The role may also be eligible for discretionary bonuses or commission payments and relocation assistance. Benefit and compensation programs are subject to eligibility requirements and applicable terms.

Requirements

Master’s degree or foreign equivalent in Electrical and Computer Engineering or a related field.
Experience and/or education in high-performance central processing unit (CPU) architecture.
Experience applying logic design principles, including timing and power implications.
Experience using C/C++ programming.
Experience using a scripting language (Python, Perl, or TCL) for data analysis and automation.
Experience with CMOS design and analysis.
Experience with the VLSI design flow, including RTL design, design verification, synthesis, and place-and-route.
Experience using lab equipment, including oscilloscopes, to take accurate, high-quality measurements.
Experience using assembly language to compose customized targeted test vectors.

Responsibilities

Generate and drive new micro-architecture and/or circuit ideas to reduce CPU power.
Drive budgeting, measurements, and analysis of CPU power for several use cases.
Work with micro-architects and physical designers to study power-reduction opportunities.
Conduct pre- and post-silicon power modeling and measurement across several use cases on current and future CPU designs.
Work with software and platform teams to optimize CPU power efficiency and use of power management features.
Drive power management feature definition and silicon tuning.