Power Engineer

Wipro•Sunnyvale, CA

About The Position

The Power Engineer owns power-analysis flows used by a large silicon team to estimate and sign off power on SoCs, from RTL to gate level. The role develops and releases in-house tools built around Synopsys power tools, supports design teams running those tools, conducts power studies on full-chip designs, and works with Synopsys to resolve tool issues. The team also uses AI agents to launch runs, debug failures, and write reports; the engineer maintains and extends these agents.

Requirements

Mandatory skill: Silicon Validation.
8–10 years of experience.

Responsibilities

Develop, maintain, and release in-house Python and Tcl wrappers around Synopsys PrimePower, PrimeTime PX, PrimePower RTL, and RTL Architect for gate-level and RTL power analysis.
Own tool releases, including versioned releases, release notes, user guides, tutorials, fixes to released versions, and user support in internal Q&A forums.
Maintain passing nightly regression suites on reference designs across process nodes and add a test for every fix.
Support design teams' power runs by setting up inputs, debugging failed runs, and assessing whether results are trustworthy.
Run power studies on large designs, including campaigns of more than 100 tests on a full-chip network-on-chip.
Derive power metrics such as energy per byte, per-block and per-power-domain attribution, clock-gating efficiency, and glitch and leakage breakdowns.
Investigate root causes of tool, library, and flow problems, including memory power rails, power-switch definitions, and PDK updates.
Build small test cases and work with Synopsys support and R&D.
Produce power data for others, including power-tracker spreadsheets, dashboards, and power maps for thermal and IR-drop tools.
Build and maintain AI-agent automation for launching and monitoring runs, analysing failures, checking inputs before expensive runs, and filing bugs automatically.