PMU Analog Layout Designer

Apple • Austin, TX

2d

About The Position

The PMU team is seeking motivated analog layout engineers at a variety of skill levels. The team develops high-performance analog IPs and complex chip-level layouts for Apple products, in a collaborative and dynamic environment with opportunities to learn and refine engineering skills. The role works closely with circuit design, integration, CAD, and circuit- and technology-engineering teams.

The designer is responsible for delivering PDV-clean layouts in deep submicron CMOS technologies. This includes planning and scheduling layout work with circuit designers, negotiating trade-offs, recognizing failure-prone circuit and layout structures, running design verification at both mega-cell and chip levels, and interpreting verification reports to complete layouts efficiently. The role uses advanced CAD tools and mask-design knowledge to produce correct, robust layouts that meet matching, area, and power requirements.

Requirements

• Bachelor’s degree.
• At least 3 years of relevant industry experience.
• Relevant experience in analog/mixed-signal layout design of submicron CMOS circuits.
• Experience building tight-matching, low-capacitance, low-power analog blocks, resistors, capacitors, high-voltage devices, pad I/Os, and ESD structures.
• Experience with custom and standard-cell-based floor planning and hierarchical layout assembly.
• Understanding of IR drop, RC delay, electromigration, self-heating, and cross-capacitance.
• Relevant experience with analog and DFM practices.
• Excellent communication skills and ability to work with multifunctional teams.
• Proficiency interpreting Calibre, DRC, ERC, LVS, and related reports.
• Knowledge of Mentor Graphics or Cadence layout tools.

Nice To Haves

• Experience in PMU and chip-level layout.
• Scripting experience in Perl or SKILL code.
• Master’s degree.

Responsibilities

• Work with circuit designers to plan and schedule work and negotiate layout trade-offs for complex analog layouts in deep submicron CMOS technologies.
• Recognize failure-prone circuit and layout structures.
• Run the complete set of available design-verification tools at mega-cell and chip levels.
• Interpret LVS, DRC, and ERC reports to identify an efficient path to layout completion.
• Work closely with circuit design teams to exceed engineering specifications and expectations.
• Use advanced CAD tools and mask-design knowledge to deliver correct and robust layouts meeting matching, area, and power requirements.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level