Physical Design Verification Manager, Annapurna Labs
About The Position
Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of Silicon and Hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for a Physical Design Verification Manager to join our backend team. The ideal candidate will be responsible for leading our Physical Design Verification Team by owning the end‑to‑end physical verification strategy for AWS’s most complex SoCs (≥100M gates), from floorplan to tape‑out.
Requirements
- BS + 10 yrs or MS + 9 yrs in EE, CS, or related field
- 8+ years in physical verification
- 5+ years managing engineers or budgets
- Expertise in Calibre, IC Validator, or PVS
- Experience in scripting languages such as Perl, Python, or Tcl
- Experience building high‑performing teams and aligning cross‑functional priorities
Nice To Haves
- Advanced‑node expertise: 5nm, 4nm, or N4P experience—especially with AWS/N4P designs
- DFM & Reliability: Deep knowledge of IR drop, EM, ESD, and parametric yield analysis
- Publications: Technical papers or presentations at DAC, ISSCC, or internal AWS forums
Responsibilities
- Own end‑to‑end physical verification strategy for AWS’s most complex SoCs (≥100M gates), from floorplan to tape‑out
- Define verification closure roadmap, resource allocation, and risk‑mitigation plans for concurrent projects
- Standardize industry‑leading verification methodologies (Calibre, IC Validator, PVS) across the organization
- Drive automation of runsets, reporting, and debug flows using Python/Perl scripts; reduce manual effort by ≥40%
- Lead a team of 3–5 Sr. PDV Engineers, setting goals, conducting quarterly reviews, and career‑pathing
- Mentor junior engineers on advanced‑node debug techniques, DFM, and reliability verification (IR drop, EM)
- Pilot next‑gen verification technologies (e.g., AI‑driven DRC, parallel cloud‑based LVS) to stay ahead of 5nm/3nm node complexities
Benefits
- health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
- 401(k) matching
- paid time off
- parental leave
- sign-on payments
- restricted stock units (RSUs)
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What This Job Offers
Job Type
Full-time
Career Level
Manager
