Design Verification

Apple • Cupertino, CA

3d • $150,400 - $225,300

About The Position

Apple Inc. is hiring for a Design Verification role in Cupertino, California, and various unanticipated locations throughout the USA. The role works closely with design and architecture teams to understand a design’s functional and performance goals and detailed features, then develop effective verification plans. It involves collaboration with design, design verification, architecture, validation, and software teams.

The position reviews specifications and develops verification plans, test benches, tests, and coverage plans to verify hardware designs. It also defines next-generation verification methodology, implements test benches and tests using SystemVerilog, UVM, and C, and writes assertions in SystemVerilog Assertion language. The role automates verification flows using Python, Perl, or other scripting languages; runs simulations using computer-aided design software; and creates, runs, and triages block-, subsystem-, or chip-level simulation regressions. The employee tracks bugs through resolution, analyzes coverage, and updates tests and constraints to close gaps. The position is 40 hours per week.

Requirements

• Bachelor’s degree or foreign equivalent in Electrical Engineering and Computer Sciences, Electrical Engineering, Electronics Engineering, or a related field.
• Use object-oriented programming principles to design and implement specified functionality.
• Use data structures, types, and algorithms to develop efficient and scalable code.
• Use computer architecture, VLSI, and logic design to understand and analyze hardware behavior.
• Use Verilog to implement test benches and test cases for hardware verification.
• Use Python to create and maintain custom scripts and internal tools for automation and reporting.
• Use C/C++ to understand, develop, and maintain system firmware code.
• Use digital logic design, interconnect network, cache, and memory architecture to understand design documentation and RTL code and develop exhaustive test plans.
• Develop ASICs and apply integrated-circuit knowledge to understand logic-design details, including timing, power, and area.
• Use a digital design simulator to run and debug RTL and power-aware simulations.

Responsibilities

• Work with design and architecture teams to understand functional and performance goals and design features.
• Collaborate with design, DV, architecture, validation, and software teams.
• Review specifications and develop verification plans, test benches, tests, and coverage plans.
• Execute plans to verify hardware designs.
• Define next-generation verification methodology.
• Implement test benches using SystemVerilog and UVM.
• Implement tests in SystemVerilog, UVM, and C according to the test plan.
• Implement assertions using SystemVerilog Assertion language.
• Automate verification flows using Python, Perl, or other scripting languages.
• Run simulations using computer-aided design software.
• Create, run, and triage block-level, subsystem-level, or chip-level simulation regressions.
• Track bugs, file reports for simulation failures, and follow issues through fix and closure.
• Analyze coverage and update tests and constraints to close gaps and achieve top results.

Benefits

• Opportunity to participate in discretionary employee stock programs.
• Eligibility for discretionary restricted stock unit awards.
• Opportunity to purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to career advancement at Apple.
• The role might be eligible for discretionary bonuses or commission payments.
• The role might be eligible for relocation.

What This Job Offers

• Job Type: Full-time