Design Verification

Apple•Cupertino, CA

About The Position

Apple Inc. is hiring for a Design Verification role in Cupertino, California, and various unanticipated locations throughout the USA. The role works closely with design and architecture teams to understand functional and performance goals and detailed design features, then develops and executes verification plans for hardware designs. It collaborates with design, design verification, architecture, validation, and software teams to review specifications and develop verification plans, test benches, tests, and coverage plans. The position also defines verification methodology, implements test benches and tests, writes assertions, automates verification flows, runs simulations, manages regressions and bugs, and analyzes coverage to close verification gaps. The position is 40 hours per week. The base pay range is $150,400–$225,300 per year, depending on skills, qualifications, experience, and location. Apple also offers eligible employees discretionary stock programs, medical and dental coverage, retirement benefits, discounted products and free services, and reimbursement for certain education expenses, including tuition. The role might also be eligible for discretionary bonuses or commission payments and relocation assistance. Benefits and compensation are subject to applicable eligibility requirements and plan terms.

Requirements

Bachelor’s degree or foreign equivalent in Electrical Engineering and Computer Sciences, Electrical Engineering, Electronics Engineering, or a related field.
Use object-oriented programming principles to design and implement specified functionality.
Use data structures, types, and algorithms to develop efficient and scalable code.
Apply computer architecture, VLSI, and logic design knowledge to understand and analyze hardware behavior.
Use Verilog to implement test benches and test cases for verifying hardware behavior.
Use Python to create and maintain custom scripts and internal tools for automation and reporting.
Use C/C++ to understand, develop, and maintain system firmware code.
Apply digital logic design, interconnect network, cache, and memory architecture knowledge to understand design documentation and RTL code and develop exhaustive test plans.
Develop ASICs and use integrated-circuit knowledge to understand logic-design details including timing, power, and area.
Use digital design simulators to run and debug RTL and power-aware simulations.

Responsibilities

Work with design and architecture teams to understand design goals and features and develop effective verification plans.
Collaborate with design, DV, architecture, validation, and software teams.
Review specifications and develop verification plans, test benches, tests, and coverage plans.
Execute plans to verify hardware designs and define next-generation verification methodology.
Implement test benches using SystemVerilog and UVM.
Implement tests in SystemVerilog, UVM, and C according to the test plan.
Implement assertions using SystemVerilog Assertion language.
Automate verification flows using Python, Perl, or other scripting languages.
Run simulations using CAD software.
Create, run, and triage block-level, subsystem-level, or chip-level simulation regressions.
Track bugs, file bug reports for simulation failures, and follow them through fix and closure.
Analyze coverage and update tests and constraints to close gaps and achieve top results.