Physical Design Staff Engineer

Synopsys•Sunnyvale, CA

49d•$129,000 - $193,000•Onsite

About The Position

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical design, where the difference between a chip that tapes out on schedule and one that doesn't often come down to a timing path you caught or a methodology decision you made six months earlier. You know that getting to signoff is not about running tools, it is about understanding what the data is telling you and building flows that make the next iteration faster and smarter. You are the engineer who looks at a timing report and sees patterns, not just violations. When a clock tree is misbehaving or a design is bleeding power, you do not just fix the symptom, you trace it back to the root cause and build something that prevents it from happening again. Automation is not a buzzword to you, it is how you scale yourself across multiple projects without losing quality. You have worked at advanced nodes where margins are thin and every decision counts. You know your way around ICC2 or Fusion Compiler well enough that you can tell when the tool is doing something unexpected, and you know how to script your way out of it. At Synopsys, you will work on real silicon with real constraints, and what you build will directly affect whether our customers can close their designs on time.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
5+ years of hands-on experience with ASIC physical design, implementation, and timing closure across block, subsystem, or chip-level designs
Deep working knowledge of static timing analysis, clock-tree synthesis, signoff flows, and ECO methodologies
Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus
Strong scripting and automation skills using TCL, Python, Perl, or similar languages to build flows and analyze data

Nice To Haves

Experience with advanced-node semiconductor design at 7nm or below is a strong plus
Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows is a plus

Responsibilities

Drive timing closure, signoff readiness, and PPA optimization for advanced-node customer designs, working across block, subsystem, and chip-level implementations
Develop and enhance physical design methodologies and automation solutions using TCL, Python, Perl, or Pandas to improve design quality, predictability, and team efficiency
Perform static timing analysis, clock-tree synthesis, and ECO implementation using tools like PrimeTime, ICC2, Fusion Compiler, or Cadence Innovus
Analyze design data and trends to identify bottlenecks, predict issues, and build flows that make the next tapeout smoother than the last
Collaborate with cross-functional engineering teams including design, verification, and CAD to ensure successful silicon delivery
Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve complex implementation challenges
Troubleshoot complex physical design problems that do not have obvious answers, and develop scalable technical solutions that work across multiple projects