Physical Design Manager

Normal Computing Corporation•Palo Alto, CA

About The Position

As Physical Design Manager at Normal Computing, you will lead the team responsible for end-to-end silicon realization, taking complex architectures from synthesis and physical floorplanning through timing signoff and GDSII tapeout. Working across custom ASIC design and hardware-algorithm co-designed systems, you will partner closely with RTL and architecture teams to assess physical feasibility early in the design cycle. You will lead backend implementation and optimize floorplanning, place-and-route, clock tree synthesis, static timing analysis, and physical verification to meet power, performance, and area targets. The role combines technical leadership and team management. It includes building and guiding the physical design team, planning work and schedules for an aggressive tapeout plan, and specifying and helping negotiate EDA tools for the physical design methodology. You will also own physical signoff, tapeout execution, and post-silicon physical debugging and bring-up as needed.

Requirements

Lead at least 3 successful tapeouts from netlist to signoff; experience across advanced technology nodes is preferred within this requirement.
Deep hands-on experience with industry-standard physical design tools, such as Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, or Calibre, across floorplanning, place-and-route, clock tree synthesis, and signoff timing closure.
Strong problem-solving skills analyzing and resolving static timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations.
Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility.
At least 7 years of managerial experience.

Nice To Haves

Experience at an AI or high-performance computing chip startup with tight design, verification, and physical design iteration cycles.
Experience with custom memory or macro floorplanning, hierarchical top-level implementation, or advanced packaging such as chiplets or 2.5D/3D integration.
Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows.

Responsibilities

Lead the physical design team, including hiring, individual guidance, and performance feedback.
Create work estimates and schedules to support an aggressive tapeout plan.
Specify and help negotiate EDA tools to support the physical design methodology.
Collaborate with RTL, architecture, and DFT teams on early floorplanning, macro placement, pin assignments, and physical feasibility.
Lead the netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis, and place-and-route.
Own static timing analysis, timing constraint creation and validation, and signoff timing closure across operating corners and modes.
Drive power, performance, and area optimization, as well as power integrity (IR/EM) and crosstalk analysis.
Execute full-chip and block-level physical signoff checks, including DRC, LVS, ERC, and antenna fixes, and ensure handoff to the foundry.
Create and execute tapeout checklists and manage final stream-out processes.
Support post-silicon physical debugging and bring-up as needed.