Physical Design Manager

Normal Computing Corporation • Palo Alto, CA

1d • $200,000 - $400,000

About The Position

Normal Computing is an applied AI company developing foundational hardware and software for the semiconductor industry, AI infrastructure, and broader systems. The company operates across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.

The Physical Design Manager leads the team responsible for the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning through timing signoff and GDSII tapeout. Working at the intersection of custom ASIC design and hardware-algorithm co-designed systems, the manager shapes physical feasibility early in the design cycle in close partnership with RTL and architecture teams. The role leads the backend implementation flow, optimizing floorplanning, place-and-route, clock tree synthesis, static timing analysis, and physical verification to meet power, performance, and area targets.

This role combines technical execution, team building, and cross-functional leadership. It requires tapeout-proven delivery, careful physical signoff, and the ability to maintain clarity during fast-paced build cycles while addressing the physical constraints of novel computing architectures.

Requirements

• Lead at least 3 successful tapeouts from netlist to signoff; experience across advanced technology nodes is preferred within this requirement.
• Deep hands-on experience with industry-standard physical design tools across floorplanning, place-and-route, clock tree synthesis, and signoff timing closure.
• Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations.
• Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility.
• At least 7 years of managerial experience.

Nice To Haves

• Experience at an AI or high-performance computing chip startup with tight design, verification, and physical design iteration cycles.
• Experience with custom memory or macro floorplanning, hierarchical top-level implementation, or advanced packaging such as chiplets or 2.5D/3D integration.
• Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows.

Responsibilities

• Lead the physical design team, including hiring, individual guidance, and performance feedback.
• Create work estimates and project schedules to support an aggressive tapeout plan.
• Specify and help negotiate EDA tools for the physical design methodology.
• Collaborate with RTL, architecture, and DFT teams on design and floorplan reviews, including early floorplanning, macro placement, pin assignments, and physical feasibility.
• Lead the netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis, and place-and-route.
• Own static timing analysis, timing-constraint creation and validation, and signoff timing closure across operating corners and modes.
• Drive power, performance, and area optimization, along with power integrity (IR/EM) and crosstalk analysis.
• Execute full-chip and block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, and ensure handoff to the foundry.
• Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed.

What This Job Offers

• Job Type: Full-time
• Career Level: Manager
• Education Level: No Education Listed