Physical Design / Implementation Lead

Neurophos • Austin, TX

2d • Onsite

About The Position

Neurophos is developing a novel AI compute architecture using silicon photonics to overcome the power limitations of traditional electronic circuits. Our technology performs matrix multiplications at the speed of light, offering significantly higher energy efficiency and performance for large-scale AI inference. We have a world-class team and recently secured $110M in Series A funding. We are seeking the first permanent Physical Design / Implementation Lead for the digital design team. This is a build role responsible for all aspects of the SoC implementation process, including building and managing a multi-site team to deliver optimized GDSII implementations. The role involves defining the RTL to tapeout process on leading-edge nodes and growing the team. This position is one of three discipline leads, alongside RTL and DV, who collectively manage digital chip development at Neurophos.

Requirements

• Track record leading physical design / implementation on large, complex SoCs through tapeout: as a back-end lead on a large SoC, or an equivalent composite of synthesis, timing closure, power, and physical-verification ownership at a senior level.
• Hands-on experience on advanced nodes; TSMC N3 strongly preferred, FinFET-class node experience (7nm–3nm) required.
• Deep power and clock design experience at scale, ideally from CPU-class or very large SoC work.
• A track record of leading and growing a team.

Nice To Haves

• Experience integrating analog/mixed-signal blocks into a digital implementation flow.
• Cadence toolchain experience.

Responsibilities

• Own physical design and implementation end-to-end, from synthesis through tapeout, on leading-edge process nodes (TSMC N3 strongly preferred; deep FinFET-class experience, 7nm–3nm, required).
• Optimize and automate our synthesis flow, and lead the intake of new process technology as we bring on new nodes.
• Optimize and automate the timing closure process at the block and subsystem level.
• Design and optimization of power and clock architecture distribution networks.
• Own the integration of analog/mixed-signal components into the digital implementation flow, building the process and working relationship between analog and digital teams.
• Own physical verification and IP/library management for the digital design org.
• Build and lead a physical design team: hire, ramp, and manage the engineers under you as the group scales.
• Work closely with the RTL/DV, Analog and other team leads on cross-functional flow and schedule decisions.

Benefits

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO.
• 401(k) matching and stock option opportunities.
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits: Choose the plans that fit your life and take the cash back for those that don’t.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed