Physical Design Engineer- Sunnyvale, CA

Cystems Logic Inc•Sunnyvale, CA
•Onsite

About The Position

The Physical Design Engineer will join a silicon engineering team supporting ASIC/SoC designs in Sunnyvale, California. The role involves work across the chip development lifecycle, with a focus on RTL synthesis, placement optimization, floorplanning, and timing closure. The position is onsite and described as a long-term contract.

Requirements

  • Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of industry experience in ASIC/SoC physical design.
  • Hands-on expertise in RTL synthesis and timing optimization.
  • Experience with floorplanning for advanced technology nodes.
  • Strong understanding of netlist optimization and physical implementation methodologies.
  • Experience collaborating with RTL/design teams to improve design quality and implementation efficiency.
  • Excellent communication and cross-functional collaboration skills.

Nice To Haves

  • Experience with industry-standard EDA tools for synthesis and physical design.
  • Strong understanding of timing, congestion, power, and area optimization techniques.
  • Experience working on high-performance CPU, GPU, AI/ML, or networking SoCs.

Responsibilities

  • Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals.
  • Perform floorplanning for complex ASIC/SoC designs while addressing timing, congestion, and power distribution.
  • Collaborate with RTL design engineers to provide feedback that improves RTL quality, synthesis results, and implementation.
  • Analyze netlists and identify opportunities to improve design quality and implementation efficiency.
  • Work with architecture, RTL, verification, and physical design teams to support design convergence.
  • Support timing closure by identifying implementation bottlenecks and recommending design improvements.
  • Participate in design reviews and contribute to process and methodology improvements.
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