Physical Design Engineer - Synth, Senior

Positron Corporation

20d • $200,000 - $300,000 • Remote

About The Position

We're looking for a Senior Physical Design Engineer - Synth to own synthesis, timing convergence, and implementation readiness for key partitions across our AI accelerator roadmap. This is a hands-on engineering role responsible for turning high-quality RTL into implementation-ready netlists, developing and maintaining timing constraints, and driving physical-aware optimization in close collaboration with RTL designers and backend implementation partners. You will be a key technical link between architecture, RTL, verification, and physical implementation, working alongside senior technical leadership to strengthen and scale our synthesis methodology.

Requirements

• 8+ years of ASIC implementation experience, including at least two successful tapeouts.
• Strong hands-on proficiency in synthesis and flow development.
• Proven experience closing timing on complex, multi-million-gate designs.
• Deep working knowledge of Cadence Genus and/or Synopsys Design Compiler.
• Strong SDC expertise, including constraint development and MMMC environments.
• A solid grasp of RTL design principles and implementation-friendly coding practices.
• Hands-on experience with advanced process nodes (7nm and below preferred).
• Strong Tcl and Python scripting ability for automation and flow development.
• Excellent debugging and root-cause analysis skills.

Nice To Haves

• Experience with AI accelerators, CPUs, or GPUs.
• Experience at 5nm and below.
• Familiarity with LPDDR, PCIe, or SerDes interfaces.
• Exposure to chiplet-based architectures and multi-clock SoC designs.
• Experience mentoring junior engineers or leading synthesis for a subsystem.

Responsibilities

• Own synthesis for assigned partitions and subsystems, delivering clean, high-QoR netlists on schedule.
• Contribute to the development and improvement of synthesis flows, including constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.
• Help define and apply signoff criteria for synthesis deliverables.
• Run hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler (or equivalent).
• Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments.
• Track and continuously improve synthesis QoR for your blocks.
• Drive logical timing closure for assigned partitions, optimizing across frequency, area, power, congestion, and wireability.
• Perform root-cause analysis of timing bottlenecks and contribute to chip-level timing budgets.
• Work with architecture and RTL teams to identify and resolve timing risks before physical implementation.
• Partner with backend implementation engineers on physical-aware synthesis, retiming, register balancing, pipeline optimization, and logic restructuring.
• Give RTL teams actionable feedback so designs are implementation-friendly from the outset.
• Collaborate with architecture, RTL, verification, physical design, DFT, IP providers, and backend design services to drive rapid issue resolution.
• Work with external implementation partners to review QoR, timing, and area reports, and support constraint methodology and acceptance criteria.
• Apply AI tools to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.

Benefits

• Fully company-paid medical, dental, and vision insurance for you and your dependents
• Company-paid life and disability coverage, with voluntary options to add more
• Supplemental hospital, critical illness, and accident coverage available
• Unlimited paid time off
• 13 paid company holidays
• Remote-first culture with a company-provided computer and home office setup
• Competitive salary and equity
• 401(k) with company matching, eligible from day one
• Visa Support (H-1B visa transfers for eligible candidates)

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed