Physical Design Engineer- Senior
Qualcomm•Austin, TX
•$115,600 - $173,400
About The Position
QCT’s DSP Team is actively seeking talented Physical Design Engineers to join our DSP PD team. As a Physical Design Engineer, you will innovate, develop, and implement DSP cores using state-of-the-art tools and technologies. This role requires strong expertise in physical design flow, tapeout readiness, and Power, Performance, and Area (PPA) optimization for advanced technology nodes. Backfill.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or related field.
- 3+ years of industry experience in Physical Design for ASIC/SoC.
- Proven tapeout experience with successful delivery of complex cores.
- Hands-on expertise with: Place & Route tools: Cadence Innovus and/or Synopsys ICC2/Fusion Compiler
- Timing closure: Synopsys PrimeTime
- Physical verification: DRC/LVS sign-off flows
- Strong understanding of DFT, multi-mode/multi-corner designs, and ECO flows.
- Proficiency in scripting languages (Perl, TCL, Python) and Linux/Unix environments.
Nice To Haves
- Experience with latest advanced technology nodes.
- Knowledge of power integrity analysis (IR-drop, EM) and low-power design techniques.
- Familiarity with formal verification , understanding of DFM and post-silicon validation .
- Ability to work in a fast-paced environment and communicate effectively with cross-functional teams.
Responsibilities
- Own and execute complete Physical Design flow from netlist to GDSII, including: Floorplanning, power planning, IR-drop analysis, Placement, MMMC clock tree synthesis, routing, Timing optimization and closure across multiple modes and corners
- Perform PPA analysis and optimization to meet aggressive power, performance, and area targets.
- Develop and enable low-power implementation methods and customized P&R strategies for area reduction and performance improvement.
- Debug timing violations, implement timing fixes, and roll in functional ECOs.
- Conduct RC extraction, signal integrity, crosstalk noise/delay analysis, and formal verification.
- Manage tapeout activities, ensuring sign-off for DRC, LVS, timing, power integrity, and reliability.
- Collaborate with RTL, architecture, and verification teams to influence design decisions for optimal PPA.
- Contribute to flow enhancements and automation using scripting (Perl/TCL, Python, Linux shell).
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Senior
