Physical Design Engineer

Intel•Folsom, CA

2d•$105,650 - $200,340•Hybrid

About The Position

As a Physical Design Engineer, you will play a pivotal role in shaping the next generation of custom IP and SoC designs at Intel. Your work will directly influence the cutting-edge technology that powers our products, driving advancements in performance, efficiency, and innovation. In this role, you will have the opportunity to engage in all aspects of physical design, from RTL to GDS, crafting a design database that is ready for manufacturing. Your expertise in optimizing designs for power, frequency, and area will contribute significantly to Intel's mission to deliver world-class technological solutions. This is an exciting opportunity to be at the forefront of physical design engineering, working alongside industry experts to push the boundaries of what is possible in semiconductor technology.

Requirements

Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field, and 3+ years of experience in physical design; OR a Master's degree in Electrical Engineering, Computer Engineering, or a related field, and 2+ years of experience in physical design; OR a PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience in RTL-to-GDS implementation, including synthesis, place and route, and timing closure.
Experience in industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics for physical design tasks.
Experience in static timing analysis, floor planning, and power integrity analysis.
Strong knowledge of low-power design techniques and methodologies.
Strong communication skills, willing to work effectively in cross-functional teams.
Enthusiasm for contributing to Intel's mission to deliver leading-edge technology and innovation.

Nice To Haves

Demonstrated experience to solve complex design challenges through innovative and efficient solutions.
Proven track record of disciplined execution and attention to detail in design implementation.
Driving continuous improvement in design methodologies and automation.

Responsibilities

Perform physical design implementation of custom IP and SoC designs from RTL to GDS.
Execute comprehensive physical design flows, including synthesis, floor planning, place and route, clock tree synthesis, static timing analysis, and power/clock distribution.
Conduct verification and signoff activities such as formal equivalence verification, static timing analysis, power integrity analysis, and layout verification.
Analyze results to identify and resolve violations related to timing, reliability, and design structure.
Optimize designs for power, performance, and area using industry-standard EDA tools.
Develop and refine physical design methodologies and flow automation to improve team efficiency and accuracy.
Collaborate with teams to address design challenges and deliver robust solutions.