Senior Physical Design Engineer (CPU)

IntelHillsboro, OR
Onsite

About The Position

Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies.

Requirements

  • Bachelors in Computer / Electrical Engineering or related field with 7+ years of relevant work experience. Or a Masters in the same field with 4+ years of relevant work experience.
  • Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
  • PV convergence (including static timing and power analysis)
  • Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
  • Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
  • Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP

Nice To Haves

  • Industry experience/exposure with CPU Micro-Architecture
  • Physical design best known practices concerning floor-planning, routing techniques, clock distribution
  • Static Timing Analysis, Noise analysis, and reliability verification techniques
  • RTL to GDS methodologies and formal equivalence
  • Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)

Responsibilities

  • Own physical design and implementation of CPU core blocks or subsystems
  • Execute synthesis, floorplanning, place and route, and design closure
  • Perform static timing analysis (STA), power analysis, and physical verification
  • Drive convergence of timing, power, and area (PPA) metrics
  • Debug and resolve complex design issues across multiple design stages
  • Develop and optimize design flows and automation scripts
  • Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams
  • Contribute to improving design methodologies and best practices
  • Provide guidance to junior engineers where applicable

Benefits

  • competitive pay
  • stock bonuses
  • health
  • retirement
  • vacation
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