Junior Physical Design Engineer (CPU)

Intel•Hillsboro, OR

23h•Onsite

About The Position

Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Junior Senior Physical Design Engineer (CPU), you will contribute to cutting-edge silicon design using advanced process technologies. You will work alongside experienced engineers to support implementation from RTL to GDS, gaining hands-on experience in high-performance, power-efficient processor design.

Requirements

Bachelors in Computer / Electrical Engineering or related field with 2+ years of educational or work experience. Or a Masters in the same field with 3+ months of educational experience.
Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
PV convergence (including static timing and power analysis)
Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)

Nice To Haves

Physical design best known practices concerning floor-planning, routing techniques, clock distribution
Static Timing Analysis, Noise analysis, and reliability verification techniques
RTL to GDS methodologies and formal equivalence
Familiar with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)
Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP

Responsibilities

Support physical design execution for CPU core or subsystem blocks under guidance
Assist with synthesis, place and route (PnR), and physical verification tasks
Perform analysis for timing, power, and design rule compliance
Debug and resolve design issues with mentorship from senior engineers
Contribute to script and flow development (e.g., TCL, Python)
Collaborate with cross-functional teams including RTL design, verification, and full-chip integration
Document design work and contribute to best practices and design flows