Physical Design Engineer/Senior Engineer level
About The Position
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drive communication and data processing transformation, helping create a smarter, more connected future for all. Qualcomm is seeking talented Physical Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects spanning high-performance computing, AI, mobile, automotive, data center, and next-generation semiconductor technologies. Engineers in this role may work on different aspects of Physical Design ASIC and SoC development, including floorplan, Clock Tree Synthesis, low power implementation, timing analysis, design methodology, automation and enabling new technology nodes. This is an excellent opportunity to join a fast-paced engineering team developing leading-edge products on advanced process technologies while collaborating with world-class design, verification, implementation, and physical design teams.
Requirements
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 2+ years of industry experience or relevant academic/project experience in Physical Design.
Nice To Haves
- ASIC/SoC Physical Design implementation.
- Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
- Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
- Physical verification and design sign-off methodologies.
- Formal verification techniques and tools.
- Power domain implementation and low-power design methodologies.
- Clock Tree Synthesis (CTS), routing, and timing optimization.
- Signal integrity, noise analysis, and MMMC sign-off flows.
- DFT-aware physical implementation and constraint management.
- Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
Responsibilities
- Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
- Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
- Perform floorplanning, partitioning, power planning, and IR-drop analysis.
- Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
- Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
- Perform RC extraction, physical verification, and formal verification activities.
- Implement engineering change orders (ECOs) and support design convergence through sign-off.
- Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
- Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
- Develop automation and productivity tools using scripting languages and software development techniques.
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Senior
